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TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
40
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
update-IR
In the Update-IR state, the new instruction is loaded into the instruction register and takes effect on the falling
edge of TCK following entry into the Update-IR state.
instruction register
The instruction register (IR) is eight bits long and specifies the instruction to be executed. Information contained
in the instruction includes: 1) the mode of operation (either normal mode, in which the device performs its normal
logic function, or test mode, in which the normal logic function is inhibited or altered), 2) the test operation to
be performed, 3) which of the four data registers is to be selected for inclusion in the scan path during
data-register scans, and 4) the source of data to be captured into the selected data register during the
Capture-DR state.
Table 11 lists the instructions supported by the TNETA1600. When in the Test-Logic-Reset state, the IR is reset
to the binary value 1000 0001, which selects the IDCODE instruction.
Table11. Instruction-Register Decoding
BINARY CODE
INSTRUCTION
SELECTED REGISTER
MODE
0000 0000
EXTEST
Boundary Scan
Test
1000 0001
IDCODE
Device Identification
Normal
1000 0010
SAMPLE/PRELOAD
Boundary Scan
Normal
0000 0011
BYPASS
Bypass
Normal
1000 0100
BYPASS
Bypass
Normal
0000 0101
BYPASS
Bypass
Normal
0000 0110
HIGHZ
Bypass
Modified Test
1000 0111
CLAMP
Bypass
Test
BYPASS
Bypass
Normal
0000 1001
BYPASS
Bypass
Normal
0000 1010
BYPASS
Bypass
Normal
1000 1011
BYPASS
Bypass
Normal
0000 1100
CELLTST
Boundary Scan
Normal
1000 1101
BYPASS
Bypass
Normal
1000 1110
BYPASS
Bypass
Normal
0000 1111
BYPASS
PRIVATE
Bypass
Normal
Private
X111 0XXX
Private
All others
BYPASS
Bypass
Normal
PRIVATE instructions are intended for manufacturing use only. These instructions may cause the
device to enter unknown states and/or operate abnormally during and after the period when the
PRIVATE instruction is active.
The descriptions of the instructions shown in Table 11 follow. Each instruction selects a test-data register in the
scan path between TDI and TDO.
EXTEST
The external test instruction allows testing of board-level interconnections. When EXTEST is the current
instruction, the boundary-scan register is selected in the scan path. TNETA1600 inputs are captured in the
boundary-scan register in the Capture-DR state. These captured values are output by shifting the register in
the Shift-DR state. Outputs of the TNETA1600 are set to a desired state by loading specific patterns (input
through TDI during the Shift-DR state) into the boundary-scan register using the Update-DR state. The device
operates in the test mode.
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