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參數(shù)資料
| 型號(hào)： | VPX3224D |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Video Pixel Decoders |
| 中文描述： | 視頻解碼器像素 |
| 文件頁數(shù)： | 17/92頁 |
| 文件大?。?/td> | 672K |
| 代理商： | VPX3224D |
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VPX 3225D, VPX 3224D
PRELIMINARY DATA SHEET
17
Micronas
2.6. Video Output Interface
Contrary to the component processing stage running at
a clock rate of 20.25 MHz, the output formatting stage
(Fig. 2–16) receives the video samples at a pixel trans-
port rate of 13.5 MHz. It supports 8 or 16-bit video for-
mats with separate or embedded reference signals, pro-
vides bus shuffling, and channels the output via one or
both 8-bit ports. Data transfer is synchronous to the in-
ternally generated 13.5 MHz pixel clock.
The format of the output data depends on three parame-
ters:
– the selected output format
YUV 4:2:2, separate syncs
YUV 4:2:2, ITU-R656
YUV 4:2:2, embedded reference codes (BStream)
– the number of active ports (A only, or both A and B)
– clock speed (single, double, half).
In 8-bit modes using only Port A for video data, Port B
can be used as programmable output.
2.6.1. Output Formats
The VPX supports the YUV 4:2:2 video format only. Dur-
ing normal operation, all reference signals are output
separately. To provide a reduced video interface, the
VPX offers two possibilities for encoding timing refer-
ences into the video data stream: an ITU-R656 com-
pliant output format with embedded timing reference
headers and a second format with single timing control
codes in the video stream. The active output format can
be selected via FP-RAM 0x150 [format].
2.6.1.1. YUV 4:2:2 with Separate Syncs/ITU-R601
The default output format of the VPX is a synchronous
16-bit YUV 4:2:2 data stream with separate reference
signals. Port A is used for luminance and Port B for chro-
minance-information. Video data is compliant to ITU-
R601. Bit[1:0] of FP-RAM 0x150 has to be set to 00. Fig-
ure 2–17 shows the timing of the data ports and the
reference signals in this mode.
Fig. 2–16:
Output format stage
O
B
O
Clock
Generation
16
8
8
8
8
8
8
Reference
Signals
Video
Samples
Port A
Port B
PIXCLK
LLC
LLC2
HREF
VREF
VACT
OE
Fig. 2–17:
Detailed data output (single clock mode)
Chrominance
(Port B)
VACT
LLC
C
1
C
n–1
C
n
Luminance
(Port A)
Y
1
Y
n–1
Y
n
PIXCLK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VPX3224E | Video Pixel Decoders |
| VPX322XE | Video Pixel Decoders |
| VQ1000J | N-Channel Enhancement-Mode MOSFET Transistor(最小漏源擊穿電壓60V,夾斷電流0.225A的N溝道增強(qiáng)型MOSFET晶體管) |
| VQ1000J | N-Channel 60-V (D-S) MOSFET |
| VQ1001J | Dual N-Channel 30-V (D-S) MOSFET with Schottky Diode |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VPX3224D-C3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| VPX3224E | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video Pixel Decoders |
| VPX3225D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video Pixel Decoders |
| VPX3225D-C3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| VPX3225E | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video Pixel Decoders |
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