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參數(shù)資料
| 型號： | VPX3224D |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Video Pixel Decoders |
| 中文描述： | 視頻解碼器像素 |
| 文件頁數(shù)： | 34/92頁 |
| 文件大?。?/td> | 672K |
| 代理商： | VPX3224D |
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PRELIMINARY DATA SHEET
VPX 3225D, VPX 3224D
34
Micronas
2.13.2. Sliced VBI Data
The sliced data mode is enabled with bit[1] of the
FP-RAM 0x138 (vbimode). This mode uses the inte-
grated data slicer (available only on VPX 3225D) and
delivers decoded data samples to the output ports.
The data slicer provides data packets of a constant size
(filled with dummy bytes). The data packets have a de-
fault size of 64 bytes. To reduce the data rate for text sys-
tems with a smaller number of data bytes, the packet
size can be reduced via FP-RAM 0x139.
During lines within the VBI-window, specified by the user
settings in the corresponding Load-Table, the VPX inter-
nally multiplexes the data slicer packets onto the lumi-
nance and chrominance outputs. Since the values 0,
254, and 255 are protected in the 8-bit output modes
(ITU-R656, BStream), each slicer sample is separated
into two nibbles for transmission. Table 2–14 shows the
implemented data formats.
In each path, one nibble is transmitted twice. The LSB
is inverted for odd parity. This assures that the values 0
and 255 will not occur (for the detection of embedded
syncs). In the mode with embedded timing event codes,
chrominance data will be limited additionally. No signifi-
cant information will be lost since only Bit 0 and 1 will be
modified. Figure 2–38 shows the timing of data and ref-
erence signals in this mode.
Table 2–14:
Splitting of sliced data to luminance and
chrominance output
Bit No.
Word
MSB
LSB
7
6
5
4
3
2
1
0
Slicer
Data
S7
S6
S5
S4
S3
S2
S1
S0
Chroma
Output
S7
S6
S5
S4
S7
S6
S5
S4
Luma
Output
S3
S2
S1
S0
S3
S2
S1
S0
The splitting described above can be disabled by setting
bit 6 in the ‘format_select’ register. In this case, the sliced
samples will be transmitted in the luminance path only.
To avoid modification of valid data, the limitation of lumi-
nance data in the 8-bit output modes should be sup-
pressed with bit 8 in the same register (note that lumi-
nance codes will not be protected).
Chrominance
(Port B)
VACT
LLC
D
1 (MSBs)
D
63 (MSBs)
D
64 (MSBs)
Luminance
(Port A)
D
1 (LSBs)
D
63 (LSBs)
D
64 (LSBs)
PIXCLK
Fig. 2–38:
Timing during lines with sliced VBI-data (single clock mode)
相關PDF資料 |
PDF描述 |
|---|---|
| VPX3224E | Video Pixel Decoders |
| VPX322XE | Video Pixel Decoders |
| VQ1000J | N-Channel Enhancement-Mode MOSFET Transistor(最小漏源擊穿電壓60V,夾斷電流0.225A的N溝道增強型MOSFET晶體管) |
| VQ1000J | N-Channel 60-V (D-S) MOSFET |
| VQ1001J | Dual N-Channel 30-V (D-S) MOSFET with Schottky Diode |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| VPX3224D-C3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| VPX3224E | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video Pixel Decoders |
| VPX3225D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video Pixel Decoders |
| VPX3225D-C3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| VPX3225E | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video Pixel Decoders |
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