參數(shù)資料
型號(hào)： VPX3224D
廠商： Electronic Theatre Controls, Inc.
英文描述： Video Pixel Decoders
中文描述： 視頻解碼器像素
文件頁(yè)數(shù)： 23/92頁(yè)
文件大?。?/td> 672K
代理商： VPX3224D
VPX 3225D, VPX 3224D
PRELIMINARY DATA SHEET
23
Micronas
2.8. Video Reference Signals
The complete video interface of the VPX runs at a clock
rate of 13.5 MHz. It mainly generates two reference sig-
nals for the video timing: a horizontal reference (HREF)
and a vertical reference (VREF). These two signals are
generated by programmable hardware and can be ei-
ther free running or synchronous to the analog input vid-
eo. The video line standard (625/50 or 525/60) depends
on the TV-standard selected with FP-RAM 0x20 [sdt].
The polarity of both signals is individually selectable via
FP-RAM 0x153.
The circuitry which produces the VREF and HREF sig-
nals has been designed to provide a stable, robust set
of timing signals, even in the case of erratic behavior at
the analog video input. Depending on the selected oper-
ating mode given in FP-RAM 0x140 [settm], the period
of the HREF and VREF signals are guaranteed to re-
main within a fixed range. These video reference signals
can therefore be used to synchronize the external com-
ponents of a video subsystem (for example the ICs of a
PC add-in card).
In addition to the timing references, valid video samples
are marked with the ‘video active’ qualifier (VACT). In or-
der to reduce the signal number of the video interface,
several 8-bit modes have been implemented, where the
reference signals are multiplexed into the data stream
(see section 2.6.1.).
2.8.1. HREF
Fig. 2–26 illustrates the timing of the HREF signal rela-
tive to the analog input. The inactive period of HREF has
a fixed length of 64 periods of the 13.5 MHz output clock
rate. The total period of the HREF signal is expressed as
nominal
and depends on the video line standard.
Analog
Video
Input
HREF
VPX
Delay
Fig. 2–26:
HREF relative to input video
4.7
μ
s (64 cycles)
nominal
2.8.2. VREF
Figs. 2–27 and 2–28 illustrate the timing of the VREF
signal relative to field boundaries of the two TV stan-
dards. The start of the VREF pulse is fixed, while the
length is programmable in the range between 2 and 9
video lines via FP-RAM 0x153 [vlen].
2.8.3. Odd/Even Information (FIELD)
Information on whether the current field is odd or even
is supplied through the relationship between the edge
(either leading or trailing) of VREF and level of HREF.
This relationship is fixed and shown in Figs. 2–27 and
2–28. The same information can be supplied to the
FIELD pin, which can be enabled/disabled as output in
FP-RAM 0x153 [enfieldq]. FP-RAM 0x153 [oepol] pro-
grams the polarity of this signal.
During normal operation the FIELD flag is filtered since
most applications need interlaced signals. After filtering,
the field type is synchronized to the input signal only if
the last 8 fields have been alternating; otherwise, it al-
ways toggles. This filtering can be disabled with FP-
RAM 0x140 [disoef]. In this case, the field information
follows the odd/even property of the input video signal.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
VPX3224D-C3 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor
VPX3224E 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video Pixel Decoders
VPX3225D 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video Pixel Decoders
VPX3225D-C3 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor
VPX3225E 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video Pixel Decoders
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