參數(shù)資料
型號(hào)： VPX3224D
廠商： Electronic Theatre Controls, Inc.
英文描述： Video Pixel Decoders
中文描述： 視頻解碼器像素
文件頁(yè)數(shù)： 25/92頁(yè)
文件大小： 672K
代理商： VPX3224D
VPX 3225D, VPX 3224D
PRELIMINARY DATA SHEET
25
Micronas
2.8.4. VACT
The ‘video active’ signal is a qualifier for valid video sam-
ples. Since scaled video data is stored internally, there
are no invalid pixel within the VACT interval. VACT has
a defined position relative to HREF depending on the
window settings (see section 2.10.). The maximal win-
dow length depends on the minimal line length of the in-
put signal. It is recommended to choose window sizes of
less than 800 pixels. Sizes up to 864 are possible, but for
non-standard input lines, VACT is forced inactive 4
PIXCLK cycles before the next trailing edge of HREF.
During the VBI-window, VACT can be enabled or sup-
pressed with FP-RAM 0x138. Within this window, the
VPX can deliver either sliced text data with a constant
length of 64 samples or 1140 raw input samples. For ap-
plications that request a uniform window size over the
whole field, a mode with a free programmable VACT is
supported [FP-RAM 0x140, vactmode]. The start and
end position for the VACT signal relative to the trailing
edge of HREF can be programmed within a range of 0
to 864 [FP-RAM 0x151, 0x152]. In this case, VACT no
longer marks valid samples only.
The position of the valid data depends on the window
definitions. It is calculated from the internal processor.
The calculated delay of VACT relative to the trailing edge
of HREF can be read via FP-RAM 0x10f (window 1) or
0x11f (window 2). Tables 2–8 and 2–9 show the formulas
for the position of valid data samples relative to the trail-
ing edge of HREF.
Fig. 2–29 illustrates the temporal relationship between
the VACT and the HREF signals as a function of the
number of pixels per output line and the horizontal di-
mensions of the window. The duration of the inactive pe-
riod of the HREF is fixed to 64 clock cycles.
Table 2–8:
Delay of valid output data relative to the trailing edge of HREF (single clock mode)
Mode
Data Delay
Data End
Video data
(HBeg+HLen)*(720/NPix)–Hlen
HBeg*(720/NPix)
for NPix < 720
for NPix
≥
720
DataDelay + HLen
Raw VBI data
150
720
Sliced VBI data
726
790
Table 2–9:
Delay of valid output data relative to the trailing edge of HREF (half clock mode)
Mode
Data Delay
Data End
Video data
(HBeg+HLen)*(720/NPix)–2*Hlen for NPix < 360
HBeg*(720/NPix)
for NPix
≥
360
DataDelay + 2*HLen
Raw VBI data
not possible!
not possible!
Sliced VBI data
662
790
HREF
LLC
DATA
(Port A or B)
PIXCLK
VACT
D
1
D
n–1
D
n
data end
data delay
64 cycles
Fig. 2–29:
Relationship between HREF and VACT signals (single clock mode)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
VPX3224D-C3 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor
VPX3224E 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video Pixel Decoders
VPX3225D 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video Pixel Decoders
VPX3225D-C3 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor
VPX3225E 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video Pixel Decoders
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