E
3.4
28F001BX
13
Deep Power-Down
The 28F001BX offers a 0.25 μW V
CC
power-down
feature, entered when RP# is at V
IL
. During read
modes, RP# low deselects the memory, places
output drivers in a high-impedance state and turns
off all internal circuits. The 28F001BX requires time
t
PHQV
(see
AC
Characteristics
—Read-Only
Operations
) after return from power-down until initial
memory access outputs are valid. After this wakeup
interval,
normal
operation
command register is reset to read array, and the
status register is cleared to value 80H, upon return
to normal operation.
is
restored.
The
During erase or program modes, RP# low will abort
either operation. Memory contents of the block
being altered are no longer valid as the data will be
partially programmed or erased. Time t
PHWL
after
RP# goes to logic-high (V
IH
) is required before
another command can be written.
3.5
Intelligent Identifier Operation
The intelligent identifier operation outputs the
manufacturer code, 89H; and the device code, 94H
for the 28F001BX-T and 95H for the 28F001BX-B.
Programming equipment or the system CPU can
then automatically match the device with its proper
erase and programming algorithms.
3.5.1
PROGRAMMING EQUIPMENT
CE# and OE# at a logic low level (V
IL
), with A
9
at
high voltage V
ID
(see
DC Characteristics
) activates
this operation. Data read from locations 00000H
and 00001H represent the manufacturer’s code and
the device code respectively.
3.5.2
IN-SYSTEM PROGRAMMING
The manufacturer and device codes can also be
read via the command register. Following a write of
90H to the command register, a read from address
location 00000H outputs the manufacturer code
(89H). A read from address 00001H outputs the
device code (94H for the 28F001BX-T and 95H for
the 28F001BX-B). It is not necessary to have high
voltage applied to V
PP
to read the intelligent
identifiers from the command register.
3.6
Write
Writes to the command register allow read of device
data and intelligent identifiers. They also control
inspection and clearing of the status register.
Additionally, when V
PP
= V
PPH
, the command
register controls device erasure and programming.
The contents of the register serve as input to the
internal state machine.
The command register itself does not occupy an
addressable memory location. The register is a
latch used to store the command and address and
data information needed to execute the command.
Erase Setup and Erase Confirm commands require
both appropriate command data and an address
within the block to be erased. The Program Setup
command requires both appropriate command data
and the address of the location to be programmed,
while the Program command consists of the data to
be written and the address of the location to be
programmed.
The command register is written by bringing WE# to
a logic-low level (V
IL
) while CE# is low. Addresses
and data are latched on the rising edge of WE#.
Standard microprocessor write timings are used.
Refer to
AC Characteristics
—Write/Erase/Program
Operations
and the
AC Waveform for Write
Operations
,
Figure
19,
parameters.
for
specific
timing
4.0 COMMAND DEFINITIONS
When V
PPL
is applied to the V
PP
pin, read
operations from the status register, intelligent
identifiers, or array blocks are enabled. Placing
V
PPH
on V
PP
enables successful program and erase
operations as well.
Device operations are selected by writing specific
commands into the command register. Table 3
defines these 28F001BX commands.
4.1
Read Array Command
Upon initial device power-up and after exit from
deep power-down mode, the 28F001BX defaults to
read array mode. This operation is also initiated by
writing
FFH
into
the
command
register.