參數(shù)資料
型號(hào)： 28F001BX
廠(chǎng)商： Intel Corp.
英文描述： 5 V Boot Block Flash Memory(5 V引導(dǎo)塊閃速存儲(chǔ)器)
中文描述： 5伏啟動(dòng)塊閃存（5伏引導(dǎo)塊閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 22/39頁(yè)
文件大?。?/td> 648K
代理商： 28F001BX
28F001BX
E
22
9.0 DESIGN CONSIDERATIONS
Flash memories are often used in larger memory
arrays. Intel provides three control inputs to
accommodate multiple memory connections. Three-
line control provides for:
a) lowest possible memory power dissipation
b) complete assurance that data bus contention
will not occur
To efficiently use these control inputs, an address
decoder should enable CE#, while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs while
deselected memory devices are in standby mode.
RP# should be connected to
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
the
system
9.1
Power Supply Decoupling
Flash memory power switching characteristics
require careful device coupling. System designers
are interested in three supply current issues;
standby current levels (I
SB
), active current levels
(I
CC
) and transient peaks producted by falling and
rising edges of CE#. Transient current magnitudes
depend on the device outputs’ capacitive and
inductive loading. Two-line control and proper
decoupling
capacitor
selection
transient voltage peaks. Each device should have a
0.1 μF ceramic capacitor connected between its
V
CC
and GND, and between its V
PP
and GND.
These high frequency, low inherent-inductance
capacitors should be placed as close as possible to
the device. Additionally, for every eight devices, a
4.7 μF electrolytic capacitor should be placed at the
array’s power supply connection between V
CC
and
GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductances.
will
suppress
9.2
V
PP
Trace on Printed Circuit
Boards
Programming flash memories, while they reside in
the target system, requires that the printed circuit
board designer pay attention to the V
PP
power
supply trace. The V
PP
pin supplies the memory cell
current for programming. Use similar trace widths
and layout considerations given to the V
CC
power
bus. Adequate V
PP
supply traces and decoupling
will decrease V
PP
voltage spikes and overshoots.
9.3
V
CC
, V
PP
, RP# Transitions and
the Command/Status Registers
Programming and erase completion are not
guaranteed if V
PP
drops below V
PPH
. If the V
PP
status bit of the status register (SR.3) is set to “1”, a
Clear Status Register command
must
be issued
before further program/erase attempts are allowed
by the WSM. Otherwise, the program (SR.4) or
erase (SR.5) status bits of the status register will be
set to “1” if error is detected. RP# transitions to V
IL
during program and erase also abort the operations.
Data is partially altered in either case, and the
command sequence must be repeated after normal
operation is restored. Device power-off, or RP#
transitions to V
IL
, clear the status register to initial
value 80H.
The command register latches commands as
issued by system software and is not altered by V
PP
or CE# transitions or WSM actions. Its state upon
power-up, after exit from deep power-down or after
V
CC
transitions below V
LKO
, is FFH, or read array
mode.
After program or erase is complete, even after V
PP
transitions down to V
PPL
, the command register
must be reset to read array mode via the Read
Array command if access to the memory array is
desired.
9.4
Power-Up/Down Protection
The 28F001BX is designed to offer protection
against accidental erasure or programming during
power transitions. Upon power-up, the 28F001BX is
indifferent as to which power supply, V
PP
or V
CC
,
powers up first. Power supply sequencing is not
required. Internal circuitry in the 28F001BX ensures
that the command register is reset to read array
mode on power-up.
A system designer must guard against spurious
writes for V
CC
voltages above V
LKO
when V
PP
is
active. Since both WE# and CE# must be low for a
command write, driving either to V
IH
will inhibit
writes. The command register architecture provides
an added level of protection since alteration of
memory contents only occurs after successful
completion of the two-step command sequences.
相關(guān)PDF資料
PDF描述
28F002BC 28F002BC 2-MBIT (256K X 8) BOOT BLOCK FLASH MEMORY
28F002BV-B 2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
28F004B3 3 Volt Advanced Boot Block Flash Memory(3 V,4M位高級(jí)引導(dǎo)塊閃速存儲(chǔ)器)
28F004S3 BYTE-WIDE SMART 3 FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT
28F004S5 BYTE-WIDE SMART 5 FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
28F001BX-B 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY
28F001BX-T 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY
28F001BX-T/28F001BX-B/28F001BN-T/BN-B 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:28F001BX-T/28F001BX-B/28F001BN-T/BN-B
28F001BX-T/B 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:28F001BX-T/B
28F002BC 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:28F002BC 2-MBIT (256K X 8) BOOT BLOCK FLASH MEMORY
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