參數(shù)資料
型號(hào)： 28F001BX
廠商： Intel Corp.
英文描述： 5 V Boot Block Flash Memory(5 V引導(dǎo)塊閃速存儲(chǔ)器)
中文描述： 5伏啟動(dòng)塊閃存（5伏引導(dǎo)塊閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 17/39頁(yè)
文件大?。?/td> 648K
代理商： 28F001BX
E
4.7
28F001BX
17
Program Setup/Program
Commands
Programming is executed by a two-write sequence.
The Program Setup command (40H) is written to
the command register, followed by a second write
specifying the address and data (latched on the
rising edge of WE#) to be programmed. The WSM
then takes over, controlling the program and verify
algorithms internally. After the two-command
program sequence is written to it, the 28F001BX
automatically outputs status register data when
read (see Figure 8, 28F001BX Byte Programming
Flowchart). The CPU can detect the completion of
the program event by analyzing the WSM status bit
of the status register. Only the Read Status
Register command is valid while programming is
active.
When
programming is complete, the program status bit
should be checked. If program error is detected, the
status register should be cleared. The internal WSM
verify only detects errors for
“1”s that do not
successfully program to “0”s. The command
register remains in read status register mode until
further commands are issued to it. If byte program
is attempted while V
PP
= V
PPL
, the V
PP
status bit
will be set to “1.” Program attempts while V
PPL
<
V
PP
< V
PPH
produce spurious results and should not
be attempted.
the
status
register
indicates
that
5.0 EXTENDED ERASE/PROGRAM
CYCLING
EEPROM cycling failures have always concerned
users. The high electrical field required by thin
oxide EEPROMs for tunneling can literally tear
apart the oxide at defect regions. To combat this,
some suppliers have implemented redundancy
schemes, reducing cycling failures to insignificant
levels. However, redundancy requires that cell size
be doubled; an expensive solution.
Intel has designed extended cycling capability into
its ETOX flash memory technology. Resulting
improvements in cycling reliability come without
increasing memory cell size or complexity. First, an
advanced tunnel oxide increases the charge
carrying ability ten-fold. Second, the oxide area per
cell subjected to the tunneling electrical field is one-
tenth that of common EEPROMs, minimizing the
probability of oxide defects in the region. Finally,
the
peak
electric
field
during
erasure
is
approximately 2 Mv/cm lower than EEPROM. The
lower electric field greatly reduces oxide stress and
the probability of failure.
The 28F001BX-B and 28F001BX-T are capable of
100,000 program/erase cycles on each parameter
block, main block and boot block.
6.0 ON-CHIP PROGRAMMING
ALGORITHM
The
programming algorithm of prior Intel Flash memory
devices on-chip, using the command register,
status register and WSM. On-chip integration
dramatically
simplifies
provides processor-like interface timings to the
command and status registers. WSM operation,
internal program verify and V
PP
high voltage
presence
are
monitored
appropriate status register bits. Figure 8 shows a
system software flowchart for device programming.
The entire sequence is performed with V
PP
at V
PPH
.
Program abort occurs when RP# transitions to V
IL
,
or V
PP
drops to V
PPL
. Although the WSM is halted,
byte data is partially programmed at the location
where programming was aborted. Block erasure or
a repeat of byte programming will initialize this data
to a known value.
28F001BX
integrates
the
Quick-Pulse
system
software
and
and
reported
via
7.0 ON-CHIP ERASE ALGORITHM
As above, the quick-erase algorithm of prior Intel
Flash memory devices is now implemented
internally, including all preconditioning of block
data. WSM operation, erase success and V
PP
high
voltage presence are monitored and reported
through the status register. Additionally, if a
command other than Erase Confirm is written to the
device after Erase Setup has been written, both the
erase status and program status bits will be set to
“1”. When issuing the Erase Setup and Erase
Confirm commands, they should be written to an
address within the address range of the block to be
erased. Figure 9 shows a system software
flowchart for block erase.
Erase typically takes 1–4 seconds per block. The
Erase Suspend/Erase Resume command sequence
allows interrupt of this erase operation to read
data
from a block other than that in which erase
is being performed
. A system software flowchart
is shown in Figure 10.
相關(guān)PDF資料
PDF描述
28F002BC 28F002BC 2-MBIT (256K X 8) BOOT BLOCK FLASH MEMORY
28F002BV-B 2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
28F004B3 3 Volt Advanced Boot Block Flash Memory(3 V,4M位高級(jí)引導(dǎo)塊閃速存儲(chǔ)器)
28F004S3 BYTE-WIDE SMART 3 FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT
28F004S5 BYTE-WIDE SMART 5 FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
28F001BX-B 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY
28F001BX-T 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY
28F001BX-T/28F001BX-B/28F001BN-T/BN-B 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:28F001BX-T/28F001BX-B/28F001BN-T/BN-B
28F001BX-T/B 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:28F001BX-T/B
28F002BC 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:28F002BC 2-MBIT (256K X 8) BOOT BLOCK FLASH MEMORY
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