參數(shù)資料
型號(hào): 28F001BX
廠商: Intel Corp.
英文描述: 5 V Boot Block Flash Memory(5 V引導(dǎo)塊閃速存儲(chǔ)器)
中文描述: 5伏啟動(dòng)塊閃存(5伏引導(dǎo)塊閃速存儲(chǔ)器)
文件頁數(shù): 7/39頁
文件大小: 648K
代理商: 28F001BX
E
28F001BX
7
Table 1. Lead Descriptions
Symbol
Type
Name and Function
A0
–A16
INPUT
ADDRESS INPUTS
for memory addresses. Addresses are internally latched
during a write cycle.
DQ0–DQ7
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS:
Inputs data and commands during memory write
cycles; outputs data during memory, status register and identifier read cycles.
The data pins are active high and float to tri-state off when the chip is deselected
or the outputs are disabled. Data is internally latched during a write cycle.
CE#
INPUT
CHIP ENABLE:
Activates the device’s control logic, input buffers, decoders and
sense amplifiers. CE# is active low; CE# high deselects the memory device and
reduces power consumption to standby levels.
RP#
INPUT
POWERDOWN:
Puts the device in deep power-down mode. RP# is active low;
RP# high gates normal operation. RP# = V
HH
allows programming of the boot
block. RP# also locks out erase or write operations when active low, providing
data protection during power transitions. RP# active resets internal automation.
Exit from deep power-down sets device to read array mode.
OE#
INPUT
OUTPUT ENABLE:
Gates the device’s outputs through the data buffers during a
read cycle. OE# is active low. OE# = V
HH
(pulsed) allows programming of the
boot block.
WE#
INPUT
WRITE ENABLE:
Controls writes to the command register and array blocks.
WE# is active low. Addresses and data are latched on the rising edge of the
WE# pulse.
V
PP
ERASE/PROGRAM POWER SUPPLY
for erasing blocks of the array or
programming bytes of each block. Note: With V
PP
< V
PPL
max, memory contents
cannot be altered.
V
CC
DEVICE POWER SUPPLY:
(5 V ±10%)
GND
GROUND
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