參數(shù)資料
型號: 28F001BX
廠商: Intel Corp.
英文描述: 5 V Boot Block Flash Memory(5 V引導(dǎo)塊閃速存儲器)
中文描述: 5伏啟動塊閃存(5伏引導(dǎo)塊閃速存儲器)
文件頁數(shù): 37/39頁
文件大?。?/td> 648K
代理商: 28F001BX
E
NOTES:
1.
Chip-enable controlled writes: write operations are driven by the valid combination of CE# and WE#. In systems where
CE# defines the write pulse width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should
be measured relative to the CE# waveform.
2.
Sampled, not 100% tested.
3.
Refer to Table 3 for valid A
IN
for byte programming or block erasure.
4.
Refer to Table 3 for valid D
IN
for byte programming or block erasure.
5.
Program and erase durations are measured to completion (SR.7 = 1). V
PP
should be held at V
PPH
until determination of
program/erase success (SR.3/4/5 = 0).
6.
For boot block programming and erasure, RP# should be held at V
HH
until determination of program/erase success
(SR.3/4/5 = 0).
7.
Alternate boot block access method.
28F001BX
37
10.8.1
PROM PROGRAMMER SPECIFICATIONS
Versions
V
CC
±10%
–120
–150
Symbol
Parameter
Notes
Min
Max
Min
Max
Unit
t
GHHEL
OE# V
HH
Setup to CE# Going Low
1, 2
480
480
ns
t
EHGH
OE# V
HH
Hold from CE# High
1, 2
480
480
ns
NOTES:
1.
2.
Sampled, not 100% tested.
Alternate boot block access method.
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