參數(shù)資料
型號(hào): 28F001BX
廠商: Intel Corp.
英文描述: 5 V Boot Block Flash Memory(5 V引導(dǎo)塊閃速存儲(chǔ)器)
中文描述: 5伏啟動(dòng)塊閃存(5伏引導(dǎo)塊閃速存儲(chǔ)器)
文件頁(yè)數(shù): 18/39頁(yè)
文件大小: 648K
代理商: 28F001BX
28F001BX
E
18
The entire sequence is performed with V
PP
at V
PPH
.
Abort occurs when RP# transitions to V
IL
or V
PP
falls to V
PPL
, while erase is in progress. Block data
is partially erased by this operation, and a repeat of
erase is required to obtain a fully erased block.
8.0 BOOT BLOCK PROGRAM AND
ERASE
The boot block is intended to contain secure code
which will minimally bring up a system and control
programming and erase of other blocks of the
device, if needed. Therefore, additional
“l(fā)ockout”
protection is provided to guarantee data integrity.
Boot block program and erase operations are
enabled through high voltage V
HH
on either RP# or
OE#, and the normal Program and Erase command
sequences are used. Reference the AC waveforms
for program/erase.
If boot block program or erase is attempted while
RP# is at V
IH
, either the program status or erase
status bit will be set to “1”, reflective of the
operation being attempted and indicating boot block
lock. Program/erase attempts while V
IH
< RP# <
V
HH
produce spurious results and should not be
attempted.
8.1
In-System Operation
For on-board programming, the RP# pin is the most
convenient means of altering the boot block. Before
issuing Program or Erase Confirm commands, RP#
must transition to V
HH
. Hold RP# at this high
voltage throughout the program or erase interval
(until after status register confirmation of successful
completion). At this time, it can return to V
IH
or V
IL
.
8.1.1
PROGRAMMING EQUIPMENT
For PROM programming equipment that cannot
bring RP# to high voltage, OE# provides an
alternate boot block access mechanism. OE# must
transition to V
HH
a minimum of 480 ns before the
initial Program/Erase Setup command and held at
V
HH
at least 480 ns after Program or Erase Confirm
commands are issued to the device. After this
interval, OE# can return to normal TTL levels.
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