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參數(shù)資料
| 型號： | 28F001BX |
| 廠商： | Intel Corp. |
| 英文描述： | 5 V Boot Block Flash Memory(5 V引導(dǎo)塊閃速存儲器) |
| 中文描述： | 5伏啟動塊閃存（5伏引導(dǎo)塊閃速存儲器） |
| 文件頁數(shù)： | 15/39頁 |
| 文件大小： | 648K |
| 代理商： | 28F001BX |
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4.3
28F001BX
15
Read Status Register
Command
The 28F001BX contains a status register which
may be read to determine when a program or erase
operation is complete, and whether that operation
completed successfully. The status register may be
read at any time by writing the Read Status
Register command (70H) to the command register.
After writing this command, all subsequent read
operations output data from the status register, until
another valid command is written to the command
register. The contents of the status register are
latched on the falling edge of OE# or CE#,
whichever occurs last in the read cycle. OE# or
CE# must be toggled to V
IH
before further reads to
update the status register latch. The Read Status
Register command functions when V
PP
= V
PPL
or
V
PPH
.
4.4
Clear Status Register
Command
The erase status and program status bits are set to
“1” by the Write State Machine and can only be
reset by the Clear Status Register command.
These bits indicate various failure conditions (see
Table 4). By allowing system software to control the
resetting of these bits, several operations may be
performed (such as cumulatively programming
several bytes or erasing multiple blocks in
sequence). The status register may then be polled
to determine if an error occurred during that series.
This adds flexibility to the way the device may be
used.
Additionally, the V
PP
status bit (SR.3), when set to
“1,”
must
be reset by system software before
further byte programs or block erases are
attempted. To clear the status register, the Clear
Status Register command (50H) is written to the
command register. The Clear Status Register
command is functional when V
PP
= V
PPL
or V
PPH
.
4.5
Erase Setup/Erase Confirm
Commands
Erase is executed one block at a time, initiated by a
two-cycle command sequence. An Erase Setup
command (20H) is first written to the command
register, followed by the Erase Confirm command
(D0H). These commands require both appropriate
command data and an address within the block to
be erased. Block preconditioning, erase and verify
are all handled internally by the Write State
Machine, invisible to the system. After receiving the
two-command erase sequence, the 28F001BX
automatically outputs status register data when
read (see Figure 9,
28F001BX Block Erase
Flowchart
). The CPU can detect the completion of
the erase event by checking the WSM status bit of
the status register (SR.7).
When the status register indicates that erase is
complete, the erase status bit should be checked. If
erase error is detected, the status register should
be cleared. The command register remains in read
status register mode until further commands are
issued to it.
This two-step sequence of set-up followed by
execution ensures that memory contents are not
accidentally erased. Also, block erasure can only
occur when V
PP
= V
PPH
. In the absence of this high
voltage, memory contents are protected against
erasure. If block erase is attempted while V
PP
=
V
PPL
, the V
PP
status bit will be set to “1”. Erase
attempts while V
PPL
< V
PP
< V
PPH
produce spurious
results and should not be attempted.
4.6
Erase Suspend/Erase Resume
Commands
The Erase Suspend command allows erase
sequence interruption in order to read data from
another block of memory. Once the erase sequence
is started, writing the Erase Suspend command
(B0H) to the command register requests that the
WSM
suspend
the
erase
predetermined point in the erase algorithm. The
28F001BX continues to output status register data
when read, after the Erase Suspend command is
written to it. Polling the WSM status and erase
suspend status bits will determine when the erase
operation has been suspended (both will be set to
“1s”).
sequence
at
a
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 28F002BC | 28F002BC 2-MBIT (256K X 8) BOOT BLOCK FLASH MEMORY |
| 28F002BV-B | 2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| 28F004B3 | 3 Volt Advanced Boot Block Flash Memory(3 V,4M位高級引導(dǎo)塊閃速存儲器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F001BX-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY |
| 28F001BX-T | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY |
| 28F001BX-T/28F001BX-B/28F001BN-T/BN-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:28F001BX-T/28F001BX-B/28F001BN-T/BN-B |
| 28F001BX-T/B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:28F001BX-T/B |
| 28F002BC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:28F002BC 2-MBIT (256K X 8) BOOT BLOCK FLASH MEMORY |
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