參數(shù)資料
型號(hào)： 28F016SC
廠商： Intel Corp.
英文描述： 16-MBIT SmartVoltage FlashFile Memory(16M位智能電壓閃速存儲(chǔ)器)
中文描述： 16兆內(nèi)存SmartVoltage FlashFile（1,600位智能電壓閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 32/42頁(yè)
文件大小： 725K
代理商： 28F016SC
BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY
E
32
PRELIMINARY
6.4
DC Characteristics
—Commercial Temperature
(Continued)
2.7 V V
CC
3.3 V V
CC
5 V V
CC
Test
Sym
Parameter
Notes Min Max Min Max Min Max Unit
Conditions
V
IL
V
IH
Input Low Voltage
7
–0.5 0.8 –0.5 0.8 –0.5 0.8
V
Input High Voltage
7
2.0 V
CC
+ 0.5
2.0 V
CC
+ 0.5
2.0 V
CC
+ 0.5
V
V
OL
Output Low Voltage
3,7
0.4
0.4
0.45
V
V
CC
= V
CC
Min
I
OL
= 2 mA (2.7V, 3.3V)
5.8 mA (5V)
V
OH1
Output High Voltage (TTL)
3,7
2.4
2.4
2.4
V
V
CC
= V
CC
Min
I
OH
= –2.5 mA
V
CC
= V
CC
Min
I
OH
= –2.5 mA
V
CC
= V
CC
Min
I
OH
= –100 μA
V
OH2
Output High Voltage
(CMOS)
3,7
0.85
V
CC
0.85
V
CC
0.85
V
CC
V
V
CC
–0.4
V
CC
–0.4
V
CC
–0.4
V
V
PPLK
V
PP
Lockout Voltage
V
PPH1
V
PP
Voltage
V
PPH2
V
PP
Voltage
V
PPH3
V
PP
Voltage
V
LKO
V
CC
Lockout Voltage
V
HH
RP# Unlock Voltage
4,7
1.5
1.5
1.5
V
3.0
3.6
V
4.5
5.5
4.5
5.5
11.4 12.6 11.4 12.6
V
2.0
2.0
2.0
V
8,9
11.4 12.6 11.4 12.6
V
Set Master Lock-Bit
Override Lock-Bit
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal V
CC
voltage and T
A
= +25
°
C. These currents are
valid for all product versions (packages and speeds).
2. I
CCWS
and I
CCES
are specified with the device de-selected. If read or written while in erase suspend mode, the device’s
current is the sum of I
CCWS
or I
CCES
and I
CCR
or I
CCW
.
3. Includes RY/BY#.
4. Block erases, programs, and lock-bit configurations are inhibited when V
PP
≤
V
PPLK
, and not guaranteed in the range
between V
PPLK
(max) and V
PPH1
(min), between V
PPH1
(max) and V
PPH2
(min), between V
PPH2
(max) and V
PPH3
(min), and
above V
PPH3
(max).
5. Automatic Power Savings (APS) reduces typical I
CCR
to 1 mA at 5 V and 3 mA at 2.7 V and 3.3 V V
CC
in static operation.
6. CMOS inputs are either V
CC
± 0.2 V or GND ± 0.2 V. TTL inputs are either V
IL
or V
IH
.
7. Sampled, not 100% tested.
8. Master lock-bit set operations are inhibited when RP# = V
IH
. Block lock-bit configuration operations are inhibited when the
master lock-bit is set and RP# = V
IH
. Block erases and programs are inhibited when the corresponding block-lock bit is set
and RP# = V
IH
. Block erase, program, and lock-bit configuration operations are not guaranteed and should not be
attempted with V
IH
< RP# < V
HH
.
9. RP# connection to a V
HH
supply is allowed for a maximum cumulative period of 80 hours.
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