參數(shù)資料
型號： 28F016SC
廠商： Intel Corp.
英文描述： 16-MBIT SmartVoltage FlashFile Memory(16M位智能電壓閃速存儲器)
中文描述： 16兆內(nèi)存SmartVoltage FlashFile（1,600位智能電壓閃速存儲器）
文件頁數(shù)： 37/42頁
文件大?。?/td> 725K
代理商： 28F016SC
E
6.6
T
A
= 0°C to +70°C
BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY
37
PRELIMINARY
AC Characteristics
—Write Operations
(1,2)
—Commercial Temperature
5 V ± 5%,
5 V ± 10% V
CC
Valid for All
Speeds
Versions
3.3 V ± 0.3 V,
2.7 V
3.6 V V
CC
Valid for All
Speeds
Unit
#
Sym
Parameter
Notes
3
Min
1
Max
Min
Max
W1
t
PHWL
(t
PHEL
)
RP# High Recovery to WE# (CE#) Going
Low
CE# (WE#) Setup to WE# (CE#) Going
Low
Write Pulse Width
Data Setup to WE# (CE#) Going High
Address Setup to WE# (CE#) Going High
CE# (WE#) Hold from WE# (CE#) High
Data Hold from WE# (CE#) High
Address Hold from WE# (CE#) High
Write Pulse Width High
RP# V
HH
Setup to WE# (CE#) Going High
V
PP
Setup to WE# (CE#) Going High
Write Recovery before Read
WE# (CE#) High to RY/BY# Going Low
RP# V
HH
Hold from Valid SRD, RY/BY#
High
V
PP
Hold from Valid SRD, RY/BY# High
1
μs
W2
t
ELWL
(t
WLEL
)
7
0
0
ns
W3
W4
W5
W6
W7
W8
W9
W10 t
PHHWH
(t
PHHEH
)
W11 t
VPWH
(t
VPEH
)
W12 t
WHGL
(t
EHGL
)
W13 t
WHRL
(t
EHRL
)
W14 t
QVPH
t
WP
t
DVWH
(t
DVEH
)
t
AVWH
(t
AVEH
)
t
WHEH
(t
EHWH
)
t
WHDX
(t
EHDX
)
t
WHAX
(t
EHAX
)
t
WPH
7
4
4
50
40
40
0
5
5
25
100
100
0
70
50
50
0
5
5
25
100
100
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
3,8
3,8
8
90
90
3,5,8
0
0
W15 t
QVVL
3,5,8
0
0
ns
NOTES:
1.
Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during
read-only operations. Refer to AC Characteristics for read-only operations.
A write operation can be initiated and terminated with either CE# or WE#.
Sampled, not 100% tested.
Refer to Table 4 for valid A
IN
and D
IN
for block erase, program, or lock-bit configuration.
V
should be held at V
(and if necessary RP# should be held at V
HH
) until determination of block erase, program,
or lock-bit configuration success (SR.1/3/4/5 = 0).
See Ordering Information for device speeds (valid operational combinations).
Write pulse width (t
) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
(whichever goes high first). Hence, t
= t
= t
= t
= t
ELWH
. If CE# is driven low 10 ns before WE# going low,
WE# pulse width requirement decreases to t
WP
– 10 ns for 5 V V
CC
WP
– 20 ns for 2.7 V and 3.3 V V
CC
writes.
Block erase, program, and lock-bit configuration with V
CC
<
3.0 V should not be attempted.
Write pulse width high (t
) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low
(whichever goes low last). Hence, t
WPH
= t
WHWL
= t
EHEL
= t
WHEL
= t
EHWL
.
2.
3.
4.
5.
6.
7.
8.
9.
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