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參數(shù)資料
| 型號(hào)： | 84C30A |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Ethernet Controller(四端口以太網(wǎng)控制器) |
| 中文描述： | 4端口以太網(wǎng)控制器（四端口以太網(wǎng)控制器） |
| 文件頁數(shù)： | 13/46頁 |
| 文件大小： | 439K |
| 代理商： | 84C30A |
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4-Port 84C30A
4-13
MD400151/C
Data Field:
The Data Field consists of 46 to 1500 bytes of
information which are fully transparent in the sense that
any arbitrary sequence of bytes may occur.
Frame Check Sequence:
The Frame Check Sequence
(FCS) field is a 32-bit cyclic redundancy check (CRC)
value computed as a function of the Destination Address
Field, Source Address Field, Type Field and Data Field.
The FCS s appended o each ransmitted rame, and used
at reception to determine if the received frame is valid.
3.2 PACKET TRANSMISSION PER PORT
The transmit data stream consists of the Preamble, four
information fields, and the FCS which is computed in real
time by the port and automatically appended to the frame
at the end of the data. The Preamble is also generated by
the port and transmitted immediately prior to the Destina-
tion Address. Destination Address, Source Address, Type
Field and Data Field are prepared in the buffer memory
prior to initiating transmission. The port encapsulates
these fields nto an Ethernet frame by nserting a preamble
prior o hese nformation ields and appending a CRC after
the information fields. A port can be programmed to
exclude nclusion of the preamble and/or the FCS from the
transmit data stream. In this case it is assumed that the
preamble and FCS are provided as part of the data written
to the port.
3.2.1 Controlling Transmit Packet Encapsulation
As was mentioned n he previous paragraph, a port can be
programmed for exclusion of the FCS and/or the preamble
when ransmitting a packet. To program a port or ransmit-
ting a packet without creating a preamble, bit #2 of the
port’s Configuration Register #1 can be written high. Once
this bit is set, all packets transmitted by the port will not
include a preamble pattern unless it is part of the data
written to the port’s transmit FIFO by the system. Similarly,
a port can be prevented from appending an FCS value to
a packet by setting bit #4 HIGH in the Configuration
Register #1. As long as this bit is high, any packet
transmitted by he port will not nclude an FCS value unless
it is written as part of the transmit data written to the port's
transmit FIFO. Appending of a FCS value can be con-
trolled on a packet per packet basis by using the
TXNOCRC pin as long as the TXNOCRC Tx-Rx Configu-
ration register bit has not been set high. If the TXNOCRC
pin is held high when the first byte of data is written to a
port's ransmit FIFO, his will prevent he port rom append-
ing a FCS value to the packet. Only those packets for
which the TXNOCRC pin is held high during the first data
write will not have an FCS value appended by the port
during transmission.
3.2.2 Transmission Initiation/Deferral
A transmission is initiated any time a double word of data
is written to the transmit FIFO. “Transmit buffer to FIFO”
transfers are coordinated via the Transmit FIFO Interface.
When the chip s not n Full Duplex mode, actual transmis-
sion of the data onto the network will only occur f the FIFO
has at least one double word of data to transmit, the
network has not been busy for the minimum defer time,
and any Backoff time requirements have been satisfied.
Following the IEEE 802.3 specifications, the minimum
defer time is measured from carrier sense going LOW to
TXEN going HIGH. The default defer time for 10Mbit/sec
serial mode s 9.6
μ
s as measured from TXEN going LOW
to TXEN going HIGH assuming that the delay from TXEN
going LOW to CSN going LOW is within 5 TXC clock
periods. When he chip s n ull duplex mode, ransmission
of data onto the network occurs independent of whether
carrier sense ndicates a busy network condition or not. To
adjust the defer time to some other value, the program-
mable defer register can be set using the formulas given n
the section describing the defer register. When transmis-
sion begins, the chip activates the transmit enable (TXEN)
line concurrently with the transmission of the first bit, of the
Preamble and keeps it active for the duration of the
transmission.
3.2.3 Collision on Transmit
On the occurrence of a transmit collision condition that
does not represent the 16th transmission attempt for the
packet or does not occur after 64 byte times into the
transmission, the controller will automatically attempt to
retransmit the packet. First, the controller will halt the
transmission of data from the FIFO and begin transmitting
a Jam pattern consisting of 55555555 hex. The controller
will also reset the Transmit FIFO read address pointer
back to the beginning of the transmit packet within the
FIFO. At the end of transmitting the Jam pattern the
controller will then begin the Backoff wait period. Once the
backoff period is finished the controller will automatically
retransmit the packet. If a packet reaches 16 retransmis-
sion attempts without success due to collisions, or if a
collision occurs ater han 64 Byte imes after he beginning
of a transmission, this s considered to represent a serious
network error. Upon any one of these two error conditions
occurring, the selected port’s Transmit FIFO will be
cleared and the corresponding TXRET output will be
driven HIGH. If the TXRET signal was driven HIGH due to
16 transmission attempts, the T16COLL signal will also be
driven HIGH. When either of the two above error condi-
tions occurs, retransmission of any packets that were in
the transmit FIFO requires first clearing the TXRET error
condition and then reloading the packet or packets in the
Transmit FIFO.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| 84C3A-A12-J06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J06L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J08L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J10L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-K06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
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