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參數(shù)資料
| 型號(hào)： | 84C30A |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Ethernet Controller(四端口以太網(wǎng)控制器) |
| 中文描述： | 4端口以太網(wǎng)控制器（四端口以太網(wǎng)控制器） |
| 文件頁數(shù)： | 4/46頁 |
| 文件大?。?/td> | 439K |
| 代理商： | 84C30A |
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4-Port 84C30A
4-4
4
MD400151/C
Pin
Pin Name
I/O
Description
36
RXRDEN
I
This is an active low input that, when driven active with the RXINTEN pin, enables
read operations from one of the four receive FIFOs within the chip.
This is an active low input that, when driven active with the TXINTEN pin, enables
write operations to one of the four transmit FIFOs within the chip.
This is the system clock acting as the chip’s read/write strobe to any of the
chips eight receive/transmit FIFO’s. With the TXINTEN and TXWREN inputs active
low, this input becomes the write strobe for writing transmit data to one of the chip’s
transmit FIFOs. Similarly, with the RXINTEN and RXRDEN inputs active low, this
input becomes the read strobe for reading receive data from one of the chips receive
FIFOs. This input must be connected to a continuous clock whose maximum
frequency can be 33 MHz.
These inputs are used to select a port’s receiver or transmitter for one of the following
operations:
1. Receive FIFO Reads
2. Transmit FIFO Writes
3. Clearing a TXRET Condition
4. Clearing a RXDC Condition
5. Aborting a Receive Packet
These are active low inputs that determine which bytes of the double word for a
receive FIFO read are driven with valid data or which bytes of a double word being
written to a transmit FIFO contain valid data.
These are active high three state outputs. When enabled, these outputs function as
a flag that indicates whether the associated port’s transmit FIFO has enough space
available to meet the threshold value programmed in the FIFO threshold register.
When enabled, a high value on any of these outputs indicates that the associated
port’s transmit FIFO has greater than or equal to the threshold number of double word
spaces available in the FIFO and a low value indicates it does not. The tristate drivers
for all these outputs are enabled by a low value on the TXINTEN input pin.
These are active high three state outputs. When enabled, these outputs function as
a flag that indicates whether the associated port’s receive FIFO has enough data
available to meet the threshold value programmed in the FIFO threshold register.
When enabled, a high value on any of these outputs indicates that the associated
port’s receive FIFO has greater than or equal to the threshold number of double
words available in the FIFO or has a completed receive packet in the FIFO as
indicated by the packets status double word being in the FIFO. The tristate drivers
for all these outputs are enabled by a low value on the RXINTEN input pin.
This is an active high output that can be used for validating reads from the receive
FIFO during a read operation and preventing over writes to the transmit FIFO during
a write operation. For further details, please refer to the Transmit Data Write timing
and the Receive Data Read timing diagrams.
This is a bidirectional pin that is used to signal the last double word of a transmit or
receive packet. During receive FIFO reads, this pin is enabled as an output and
when detected high indicates that the last double word of a receive packet has been
read from the receive FIFO. During transmit FIFO writes, this pin is an input and when
asserted high during a write it indicates that this is the final double word of a transmit
packet. In the transmit FIFO write case, the value of this signal is stored as the 33rd
bit in the FIFO. In the receive FIFO read case, the value of this signal is read out as
the 33rd bit of the receive FIFO.
37
TXWREN
I
35
RXRD_TXWR
I
30, 29
RXTXPS[1:0]
I
23, 24
25, 26
RXTXBE[3:0]
I
44, 57
64, 73
TXRDY_[1:4]
O
42, 56
63, 72
RXRDY_[1:4]
O
39
SPDTAVL
O
40
RXTXEOF
I/O
Pin Description (cont.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 850-10-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 854-10-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 852-10-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 852-90-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 852-90-016-10-002 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 84C3A-A12-J06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J06L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J08L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J10L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-K06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
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