參數(shù)資料
型號(hào)： 84C30A
廠商： LSI Corporation
英文描述： 4-Port Ethernet Controller(四端口以太網(wǎng)控制器)
中文描述： 4端口以太網(wǎng)控制器（四端口以太網(wǎng)控制器）
文件頁(yè)數(shù)： 26/46頁(yè)
文件大?。?/td> 439K
代理商： 84C30A
4-Port 84C30A
4-26
MD400151/C
EOF on Data Bit 2
This function puts a HIGH EOF value on both the last
double word of data and the status double word.
Multicast Mode
Each port has a 64 bit multicast address filter register
which can be accessed as shown in the Internal Port
Register Addressing Table (page 18). When a port is
programmed to receive multicast frames (match mode 3),
after computing the CRC on the address field of the
receiving frame (first 6 bytes), it will index to the multicast
address filter register depending on bits 0 to 5 of the CRC.
If the corresponding bit is a ‘1’ it will receive the frame,
otherwise it will discard the frame.
Configuration Register #1
Allows for control of a port’s various transmit and receive
features. Set to all 0’s after reset.
Group Address Mode
In this mode the ast 4 bits of the serial receive data stream
for the destination address are masked out in address
comparison. This means that when the destination ad-
dress is compared against the value programmed in the
station address register that the packet will not be rejected
due to incorrect address even its last 4 bits did not match.
Transmit Packet Autopad Mode
This feature automatically pads packets to be transmitted
with less than 60 bytes of data out to a minimum IEEE
802.3 standard packet length of 60 bytes excluding FCS.
Padding is done with bytes of 00 hex.
Transmit No Preamble Mode
This mode prevents the transmitter from adding a pre-
amble pattern at the beginning of data to be transmitted.
Disable Loopback Mode
Description on the Loopback mode (Bit #3 of Config 1)
The following description assumes that a transceiver is
connected to the MAC.
Configuration Register #1
Bit 3
1
Bit 5
0
(Deful)
Mode
Half
Duplex
Functional Description
In this mode, the transmit
data looped back from the
transceiver is ignored by
the controller. The data
does not get written into
the receive FIFO and the
Rxrdy does not reflect the
incoming data.
0
(Deful)
1
Full
Duplex
In this mode, the
transceiver (In Full Duplex
mode), will not loopback
the transmitted data.
However, since data
reception is possible during
transmission, bit 3 should
be written with ‘0’ so that
the data gets written to the
Receive FIFO.
Half Duplex Mode
Bit 3 = ‘1’, Bit 5 = ‘0’
In this mode, the transmit data looped back from the
transceiver (connected to a port of the 84C300) is ignored
by the controller. The data does not get written into the
receive FIFO and the Rxrdy does not reflect the incoming
data.
7
6
5
3
2 1
4
0
Bit 0 = ‘1’ Enables Group
Address Mode
Bit 1 = ‘1’ Enables Transmit
Packet Autopad Mode
Bit 2 = ‘1’ Enables Transmit No
Preamble Mode
Bit 3 = ‘1’ Receive Own Transmit
Disable Mode
Bit 4 = ‘1’ Enables Transmit No
CRC Mode
Bit 5 = ‘1’ Enables Full Duplex
Mode
[Bit 3 Should be ‘0’]
Bit 6 = ‘1’ Enables Receive CRC
Mode
Bit 7 = ‘1’ Disables Receive Interrupt’s
相關(guān)PDF資料
PDF描述
850-10-016-10-001 PCB connectors 1.27 mm Single row / double row / triple row Solder tail
854-10-016-10-001 PCB connectors 1.27 mm Single row / double row / triple row Solder tail
852-10-016-10-001 PCB connectors 1.27 mm Single row / double row / triple row Solder tail
852-90-016-10-001 PCB connectors 1.27 mm Single row / double row / triple row Solder tail
852-90-016-10-002 PCB connectors 1.27 mm Single row / double row / triple row Solder tail
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
84C3A-A12-J06 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C3A-A12-J06L 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C3A-A12-J08L 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C3A-A12-J10L 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C3A-A12-K06 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
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