- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378230 > 84C30A (LSI Corporation) 4-Port Ethernet Controller(四端口以太網(wǎng)控制器) PDF資料下載
參數(shù)資料
| 型號： | 84C30A |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Ethernet Controller(四端口以太網(wǎng)控制器) |
| 中文描述： | 4端口以太網(wǎng)控制器（四端口以太網(wǎng)控制器） |
| 文件頁數(shù)： | 5/46頁 |
| 文件大?。?/td> | 439K |
| 代理商： | 84C30A |
第1頁第2頁第3頁第4頁當(dāng)前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
4-Port 84C30A
4-5
5
MD400151/C
Pin
Pin Name
I/O
Description
41
TXNOCRC
I
This active high input is used to control appending of a CRC to a transmit packet.
A transmit packet can be made to exclude appending a CRC value if this input is held
high during the first double word write of transmit data to the transmit FIFO.
Transmission of all packets without CRC can be done by setting bit #4 of configura-
tion register #1. It should be noted that TXNOCRC pin can be used to control CRC
encapsulation only on a per packet basis.
This is the bidirectional 32 bit data bus for reads or writes to the chips receive or
transmit FIFO's. For receive FIFO reads it is enabled as an output with the assertion
of the RXINTEN, RXRDEN, and a low value on the RXRD_TXWR input strobe.
Otherwise it is used as an input.
80-84
86-89
91-94
96-101
107-112
115-121
RXXDAA[31:0]
I/O
Transmit and Receive Exception Indicators
48, 62
71, 79
TXRET_[1:4]
O
These are active high tristate outputs. All four of these output pins are driven by
tristate drivers enabled by an active low being driven onto the TXINTEN input pin.
Once enabled, a high value on any of these inputs indicates that the associated port
could not complete transmission of a packet due to one of the following conditions
and that a retransmission of the packet is requested:
1. A late collision occurred during transmission.
2. Carrier sense never went high or dropped out
during transmission.
3. During a transmission attempt a transmit FIFO underflow error occurred.
4. 16 attempts to transmit the packet all resulting in transmit collisions.
Internally, the TXRET signal will remain high until it is cleared by the CLRTXERR pin,
(See the text on clearing error conditions). As long as the internal TXRET signal for
a port remains high, that port’s transmit FIFO will remain cleared and no new
transmissions can occur.
These are active high tristate outputs. All four of these outputs pins are driven
by tristate drivers enabled by a low value being driven onto the RXINTEN input pin.
Once enabled, a high value on any of these inputs indicates that the associated port’s
discarded reception of a packet due to one of the possible receive discard conditions.
Internally, a port’s RXDC signal will remain high until it is cleared by the CLRRXERR
pin, (See the text on "Receive Discard Conditions"). As long as the internal RXDC
signal for a port remains high, that port’s receive FIFO will remain cleared and no new
packets will be received.
45, 58
65, 74
RXDC_[1:4]
O
Special Purpose Pins
38
CLRTXERR
I
This active high input is used to clear transmit retry flags within the chip. See the
"Receive Discard Conditions" section for how this input is used.
This active high input is used to clear Receive Discard flags within the chip. See the
"Receive Discard Conditions" section for how this input is used.
This input when pulsed high causes port #1 to abort reception of a receive frame and
clear the Receive FIFO. It can be asserted at any time during the reception of a
frame.
This input when pulsed high causes port #2 to abort reception of a receive frame and
clear the Receive FIFO. It can be asserted at any time during the reception of a
frame.
50
CLRRXERR
I
46
RXABORT_1
I
59
RXABORT_2
I
Pin Description (cont.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 850-10-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 854-10-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 852-10-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 852-90-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 852-90-016-10-002 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 84C3A-A12-J06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J06L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J08L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J10L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-K06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。