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參數(shù)資料
| 型號： | 84C30A |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Ethernet Controller(四端口以太網(wǎng)控制器) |
| 中文描述： | 4端口以太網(wǎng)控制器（四端口以太網(wǎng)控制器） |
| 文件頁數(shù)： | 25/46頁 |
| 文件大?。?/td> | 439K |
| 代理商： | 84C30A |
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4-Port 84C30A
4-25
MD400151/C
Clearing Interrupts
Both receive and transmit interrupts for a port are com-
bined into a single interrupt signal which then goes to that
port's INT output pin. The interrupt signal within a port in
the chip is actually the result of the receive/transmit status
register outputs and the receive/transmit command regis-
ter interrupt enable bits that are set. To clear an interrupt
the status that caused the interrupt needs to be cleared.
This can be accomplished by reading the transmit status
register and/or the receive status register.
3.6.7 Configuration Register #2
Allows for control of a port’s transmission of one packet at
a time, Busmode, Multi-cast hash filter, reception of runt
frames, and halting new transmissions until one of the
port’s transmit status registers is cleared.
7
6 5
3
2
1
4
0
Bit 1 = ‘1’ Disables
New Transmissions
Upon Full TX
Status Registers
Bit 2 = ‘1’ Sets a High
Value of EOF as the 33rd
Bit on Both the Last
Double Word of Data and
the Status Double Word
Bit 3 = ‘1’ Enables
Hash Filter for Multicast
Bit 4 = ‘1’ Enables Packet
Reception Without
Discard Even if the
RXABORT Goes High
During Reception
Bit 5 =
Bit 0 = ‘1’ Disable
Loads to Transmit
Status Reg. Upon
Transmission
Successful
Write = ‘1’ Packs Only 2
Bytes into the First
Double Word Written to
the Receive FIFO
Read = ‘1’ SQE Status
Bit 7 = ‘1’ Sets Port’s
FIFO Interfaces to Big
Endian Mode.
Bit 6 = ‘1’ If this bit is set,
whenever the EOF is written
to the Transmit FIFO for a
transmit packet, the TXRDY is
driven low until the packet has
completed transmission.
Don’t Load Tx Status Upon Successful Transmit Mode
If bit #0 of configuration register #2 s set, hen a packet hat
has been transmitted successfully will not have it’s status
loaded into either of the two internal transmit status regis-
ters.
Disable Further Transmission Upon Full Tx Status
Register Mode
If bit #1 of configuration register #2 is set, whenever both
Tx Status Registers have been filled, no new transmis-
sions will occur until one of the Tx Status Registers is
cleared, even if the transmit FIFO has transmit data.
Successful Packet Transmission Complete Feature
This feature is programmable by setting bit 7 of configura-
tion register #2 to a ‘1’ value. If this bit is set, then,
independent of the FIFO threshold setting, the corre-
sponding port’s TXRDY pin will go LOW once the final
double word of data for a transmit packet is written to the
transmit FIFO. Once a port’s TXRDY has been driven
LOW due to this condition, it will remain LOW until the
packet has completed transmission without error or until a
transmission exception condition causing the TXRET pin
to go HIGH is cleared. This allows the user to determine
when a packet has completed successful transmission by
detecting when the corresponding port’s TXRDY goes
HIGH after the final double word of the packet has been
written. After TXRDY goes LOW due to a double word
write with the RXTXEOF pin HIGH, further writes to the
transmit FIFO are allowed as long as the SPDTAVL pin
indicates that there is still space available within the
transmit FIFO.
Big Endian Mode
Writing this bit HIGH programs the port to Big Endian
mode.
Pack Only Two Valid Bytes in First Receive Double
Word, Bit 5
This s a read/write bit. When read, t ndicates SQE status,
the SQE function is always on, when reading this register
it causes it to reset. If this bit is set then the first double
word of data written to the receive FIFO for a receive
packet will have only two valid bytes. When this first
double word is read out of the receive FIFO , which two
bytes are valid depends upon whether the port has been
programmed for Big Endian or Little Endian mode. For the
first double word read, only RXTXDATA[15:0] are valid if
bit #6 is HIGH, otherwise only RXTXDATA[31:16] are
valid. All subsequent double words of data read from the
receive FIFO will contain 4 valid bytes except for the last
double word which may not have all 4 bytes valid.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 850-10-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 854-10-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 852-10-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 852-90-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 852-90-016-10-002 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 84C3A-A12-J06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J06L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J08L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J10L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-K06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
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