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參數(shù)資料
| 型號： | 84C30A |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Ethernet Controller(四端口以太網(wǎng)控制器) |
| 中文描述： | 4端口以太網(wǎng)控制器（四端口以太網(wǎng)控制器） |
| 文件頁數(shù)： | 3/46頁 |
| 文件大?。?/td> | 439K |
| 代理商： | 84C30A |
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4-Port 84C30A
4-3
3
MD400151/C
Pin
Pin Name
I/O
Description
Chip Registers’ Interface
22
ENREGIO
I
This active low input enables the chip for register operations. This input must be
low before any port’s registers can be written or read.
For a selected port within the chip, this input acts as a write strobe for one of the port’s
registers. The port is selected through the REGPS[1:0] inputs and the register is
addressed through the A[2:0] address inputs. The data being written appears on the
CDST[7:0] data lines and must be set up relative to the rising edge of the write strobe.
This input is active low.
For a selected port within the chip, this input acts as a read strobe for one of the port’s
registers. The port is selected through the REGPS[1:0] inputs and the register is
addressed through the A[2:0] address inputs. When the read strobe is active low,
the output drivers for CDST[7:0] data bus are enabled. Valid register data appears
on the data bus a specified time before the rising edge of the read strobe.
These inputs are used to select which port’s registers are read or written by asserting
the RD or WR read or write strobe inputs. Binary values of 00 through 11 select
channels 1 through 4 respectively with REGPS1 being the MSB of the binary value.
These inputs are the address lines used to select which register within a port is being
read or written. A3 has an internal pull down.
These bidirectional lines carry register data to or from the internal registers of each
port in the chip. These lines are nominally high impedance until their output drivers
are enabled by the RD and ENREGIO input pins being driven low.
This output is driven high by a variety of port #1 transmit and receive interrupt
conditions. It remains high until the port #1 status register containing the reason for
the interrupt is read.
This output is driven high by a variety of port #2 transmit and receive interrupt
conditions. It remains high until the port #2 status register containing the reason for
the interrupt is read.
This output is driven high by a variety of port #3 transmit and receive interrupt
conditions. It remains high until the port #3 status register containing the reason for
the interrupt is read.
This output is driven high by a variety of port #4 transmit and receive interrupt
conditions. It remains high until the port #4 status register containing the reason for
the interrupt is read.
This input is an active low chip reset. During reset all registers are reset to zero, all
FIFO’s are cleared, all counters are reset to zero, and all the inputs to the output
drivers for the RXDC and TXRET outputs are driven high.
4
W R
I
5
RD
I
21, 20
REGPS[1:0]
I
153,
6, 7, 8
5-8
9-12
A[3:0]
I
CDST[7:0]
I/O
7
INT_1
O
61
INT_2
O
68
INT_3
O
77
INT_4
O
49
RESET
I
Receive and Transmit FIFO Interface
31
RXINTEN
I
This is an active low input that acts as a chip enable to enable the receiver interface.
Driving this pin active enables the output drivers for the RXDC_1, RXDC_2,
RXDC_3, RXDC_4, RXRDY_1, RXRDY_2, RXRDY_3, and RXRDY_4 pins. Also,
this pin must be driven active before receive FIFO reads can be performed.
This is an active low input that acts as a chip enable to enable the transmitter
interface. Driving this pin active enables the output drivers for the TXRET_1,
TXRET_2, TXRET_3, TXRET_4, TXRDY_1, TXRDY_2, TXRDY_3, and TXRDY_4
pins. Also, this pin must be driven active before transmit FIFO writes can be
performed.
32
TXINTEN
I
1.0 Pin Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 850-10-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 854-10-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 852-10-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 852-90-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 852-90-016-10-002 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 84C3A-A12-J06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J06L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J08L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J10L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-K06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
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