參數(shù)資料
型號(hào)： 84C30A
廠商： LSI Corporation
英文描述： 4-Port Ethernet Controller(四端口以太網(wǎng)控制器)
中文描述： 4端口以太網(wǎng)控制器（四端口以太網(wǎng)控制器）
文件頁(yè)數(shù)： 22/46頁(yè)
文件大小： 439K
代理商： 84C30A
4-Port 84C30A
4-22
MD400151/C
3. A transmit error condition occurred i.e,
(Carrier sense never went active during
transmission or went from an active to nactive state
during transmission or 16 collisions occurred for a
transmit packet or a late collision occured).
4. The packet was transmitted successfully.
Interrupts are cleared by following the procedure given in
the section entitled "Clearing Interrupts".
Bit 4 is used for testing purposes and
should not be
written high under normal circumstances.
Bits 5 and 6 are used n conjunction with he A[2:0] address
pins to access registers other than the Receive and
Transmit Command and Status Registers within a port.
(See the Internal Port Register Addressing table).
Bit 7 is used for testing purposes and
should not be
written high under normal circumstances.
Transmit Command Register Format
A delay ime after he highgoing edge of he read operation
that reads new transmit status, one of the nternal transmit
status registers will be cleared and made available for new
transmit status. Following are the types of transmit status
given through status register:
Bit 0 - Transmit FIFO Underflow Occurred
Bit 1 - Collision during transmission occurred.
Bit 2 - 16 collisions occurred while attempting to
transmit a packet.
Bit 3 - Packet transmitted successfully.
Bit 4 - Carrier Sense error during transmission
attempt.
Bit 5 - Transmit Deferred Due to Carrier Sense.
Bit 6 - Late Collision
Bit 7 - Old/New Status.
Bit 5 of the Transmit status register (transmit OK but defer)
is an indication that the transmit state machine was ready
to initiate a transmission but it has to defer due to carrier
sense being HIGH. Bit 6 of the Transmit status register
(Late Collision) is an indication that the transmitter en-
counter a collision contention 64 byte times after TXEN
when HIGH.
A port can be programmed so hat f both ransmit registers
are full, no new transmissions will occur until at least one
of the register is cleared by reading it. To program this
feature, bit #1 of configuration register #2 needs to be
written to a 1 value.
Also a port can be programmed so that no new transmit
status is loaded if the transmission is successful.
Transmit Status Register Format
3.6.4 Transmit Status Register
Within each port's transmit section are 2 transmit status
registers. These registers give the appearance of a single
register to an external CPU. With each transmission at-
tempt, whether successful or not, one of the status regis-
ters is written with the transmit status for that packet and
bit 7 of that register is set to a 0 until both registers are full.
When both registers are full, no new transmit status can be
written until one of the registers is read. To an external
CPU, both transmit status registers appear as a single
register. If the CPU reads a LOW value for bit 7 of the
transmit status register, this indicates that either one or
both of the nternal transmit registers contains new status.
Interrupt on Transmit Underflow
Interrupt on Transmit Collision
Tx Error Condition
Interrupt on Transmission
Successful
7
6
5
3
2
1
4
0
0
0
0
0
BIT
Values After Reset
Test Mode
Register Code Bit 0
Register Code Bit 1
Test Mode
0
0
0
0
Transmit Underflow
Transmit Collision
16 Transmission Attempts
Transmission Successful
7
6
5
3
2 1
4
0
BIT
Old/New Status
Carrier Sense Error During
Transmission
Transmit OK But Defer
Late Collision
相關(guān)PDF資料
PDF描述
850-10-016-10-001 PCB connectors 1.27 mm Single row / double row / triple row Solder tail
854-10-016-10-001 PCB connectors 1.27 mm Single row / double row / triple row Solder tail
852-10-016-10-001 PCB connectors 1.27 mm Single row / double row / triple row Solder tail
852-90-016-10-001 PCB connectors 1.27 mm Single row / double row / triple row Solder tail
852-90-016-10-002 PCB connectors 1.27 mm Single row / double row / triple row Solder tail
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
84C3A-A12-J06 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C3A-A12-J06L 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C3A-A12-J08L 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C3A-A12-J10L 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C3A-A12-K06 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*