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參數(shù)資料
| 型號： | 84C30A |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Ethernet Controller(四端口以太網(wǎng)控制器) |
| 中文描述： | 4端口以太網(wǎng)控制器（四端口以太網(wǎng)控制器） |
| 文件頁數(shù)： | 16/46頁 |
| 文件大小： | 439K |
| 代理商： | 84C30A |
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4-Port 84C30A
4-16
MD400151/C
3.3.3 Terminating Reception
Reception is terminated when either of the following con-
ditions occur:
Carrier Sense or Receive Data Valid Inactive:
Indicates
that traffic is no longer present on the Ethernet cable.
Overflow:
The host node for some reason is not able to
empty a port Receive FIFO as rapidly as it is filled, and an
error occurs as frame data is lost. On average a port’s
Receive FIFO must be serviced every 3200 ns o avoid his
condition.
3.3.4 Using the RXABORT Pins to Terminate
Reception of a Packet
By pulsing the corresponding RXABORT pin high for a
minimum of 1.5 RXC cycles, reception of a packet by a port
can be terminated. When reception of a packet is termi-
nated this way, the Receive FIFO will be cleared and will
stay cleared until carrier sense transitions from high to ow
or from low to high indicating either the end of the packet
being aborted or the beginning of a new receive packet. It
is important to note that RXABORT will cause the RXDC
pin to go high based on the conditions described under
“Conditions that cause the RXDC pin to go high”.
The assertion of RXDC s done so that an external proces-
sor will always have an indication of a packet abortion
irrespective of whether it’s aborted by the user or by an
external PHY. However, the assertion of the RXDC signal
can be avoided by setting bit 4 of configuration register #2.
This will enable the reception of any packet irrespective of
errors and also reduce the number of signals (RXDC1_4
and CLRRXERR) that need to be processed when the
corresponding RXABORT goes high.
3.3.5 Receive Discard Conditions
Receive packets can be discarded for not meeting the
minimum IEEE 802.3 requirements for a good packet, for
address mismatches when the chip is not in promiscuous
mode, and by user intervention. In the case of discards
due to oversized packets, address mismatches, or the
assertion of the RXABORT pin during packet reception,
further writing of receive packet data to the receive FIFO
is halted once the mismatch, receive abort or oversized
packet condition is determined.
Except for discards due to address mismatches and over-
sized packets, all packet discards occur after carrier sense
deasserts. The discarding of receive packets for error
conditions can be controlled through bits 0 through 3 of the
receive command register, and through bit 4 of configura-
After computing the FCS on the first six bytes of the
address field (Destination address), a port uses bits 0 thru
5 as an address to its Multi-cast address filter register. Bit
0 of the FCS is assumed to be where receive data enters
the FCS generation circuitry. If the corresponding bit
addressed n the Multicast address filter register s a 1’ the
port will receive the frame, otherwise it will discard the
frame. Addressing of the Multicast address filter register
occurs using bits 0 thru 2 to determine which byte is
selected and bits 3 thru 5 to determine which bit according
to the following tables:
FCS Bits
3
4
Bit Selected
5
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
FCS Bits
0
1
Byte Selected
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Multicast Address:
If the first bit of the incoming address
is a 1 and the port is programmed to accept Multicast
Addresses without using Hash filtering, the frame is re-
ceived. A port also can be programmed to use the hash
filter for determining acceptance of multicast addresses.
Broadcast Address:
The six incoming destination ad-
dress bytes must all be FF hex. If a port is programmed to
accept Broadcast or Multicast Addresses the frame will be
received.
If the incoming frame is addressed to a port in the chip
specifically (Destination Address matches the contents of
the Station Address Register), or is of general or group
interest (Broadcast or Multicast Address), the port will
pass the frame exclusive of Preamble and FCS to the CPU
buffer and indicate any error conditions at the end of the
frame. If, however, the address does not match, as soon
as the mismatch is recognized, the port will terminate
reception and issue an RxDC.
A port may be programmed via the Match Mode bits of the
Receive Command Register to ignore all frames (Disable
Receiver), accept all frames (Promiscuous mode), accept
frames with the proper Station Address or the Broadcast
Address (Station/Broadcast), or accept all frames with the
proper Station Address, the Broadcast Address, or all
Multicast Addresses (Station/Broadcast/Multicast).
相關(guān)PDF資料 |
PDF描述 |
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| 850-10-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 854-10-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 852-10-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 84C3A-A12-J06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J06L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J08L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J10L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-K06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
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