參數(shù)資料
型號(hào)： 84C30A
廠(chǎng)商： LSI Corporation
英文描述： 4-Port Ethernet Controller(四端口以太網(wǎng)控制器)
中文描述： 4端口以太網(wǎng)控制器（四端口以太網(wǎng)控制器）
文件頁(yè)數(shù)： 27/46頁(yè)
文件大小： 439K
代理商： 84C30A
4-Port 84C30A
4-27
MD400151/C
Full Duplex Mode
Bit 3 = ‘0’, (default), Bit 5 = ‘1’
In this mode, the transceiver (in Full Duplex mode), will not
loopback the transmitted data. However, since data
reception is possible during transmission, bit 3 should be
written with a value of 0’ so that the data gets written to the
receive FIFO.
Transmit No CRC Mode
This mode prevents a port’s transmitter from appending
transmit data with an FCS.
Full Duplex Mode
In this mode a ports transmitter will ignore carrier sense
and will not defer to it if it is ready to transmit a packet.
The software bit setting and the hardware setting (pin
#108) have an OR relationship. This means that either the
hardware or software setting will enable Full Duplex.
Receive CRC Mode
In this mode a ports receiver loads the 4 bytes of FCS into
the receive FIFO along with the data allowing the FCS
value to be read out.
Disable Receive Interrupts
With this bit set, a port’s receiver is disabled from produc-
ing receive interrupts.
3.6.8 FIFO Threshold Register
This register allows programming of the threshold of
Space Available and/or Data Available double word
counts that cause assertion of the TxRDY and/or RxRDY
signals respectively. Bits 4 through 7, when written with a
binary value, indicates the minimum number of double
words necessary in the receive FIFO before RxRDY is
asserted. Similarly, bits 0 through 3, when written with a
binary value, ndicate he minimum number of double word
wide spaces necessary in the transmit FIFO for TxRDY to
be asserted. On page 28 is a table showing how many
double words of space/data are required to cause the
TXRDY/RXRDY signals to go high for each threshold
setting.
3.6.9 Defer Register Calculations for the 84C30A
Defer Time Definitions
In the standard Half Duplex Mode, Defer time s defined as
the time from the falling edge of carrier sense to the rising
edge of TXEN. In full duplex mode, the defer time is
measured as the time from the falling edge of TXEN to the
next rising edge of TXEN. The binary value programmed
into he defer count register s used o determine how many
byte times the defer time will be set to. The algorithms
below illustrates how the defer time is calculated.
Algorithm for Defer Time Calculations for 10 Mbit
Serial Mode
Defer Time = Int {{Int(Delay/100)+17+DefRegSet}/8}+2
Defer Time = The transmit defer time in byte times
Delay =
Delay from the down going edge of TXEN to the
down going edge of CSN. (Half Duplex)
= 0 (Full Duplex)
DefRegSet = The transmit defer register setting
Int = Using the Whole Number Portion
Example Calculations
To find out the value that needs to be programmed
into the defer register for a defer time of 9600 ns, the
following steps need to be taken
Assume Delay = 3400 ns
Desired Defer Time = 9600 ns = 12 byte times
The desired byte times should be a multiple of 800
Step 1: Calculation of the Actual Defer Time
Let’s assume a Defer Register Setting Value of 21
Defer Time = Int { { Int (Delay / 100) + 17 + DefRegSet}
/8} + 2
= Int { { Int (34) + 17 + 21}/8} + 2
= Int {9} + 2
= 9 + 2 = 11 byte times
Step 2: Calculation of the Actual Defer Register
Setting
Since we know that the value derived from the
previous step is 1 byte time lower than what is
desired we will increment the assumed defer
register setting by 8 and do the calculations again.
Let’s assume a Defer Register Setting Value of 29
Defer Time = Int {{Int (Delay / 100)+17+DefRegSet}
/8} + 2
= Int { { Int (34) + 17 + 29 } /8} + 2
= Int { 10 } + 2
= 10 + 2 = 12 byte times
Please note that you might have to do this process
several times before you can get the actual defer
register setting for a desired defer time based on your
delays.
3.6.10 Transmit Control/Product I.D. Register
The ower four bits can be used to set a threshold value on
the transmit FIFO that can be used to control the packet
transmission and the upper four bits of this register con-
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84C3A-A12-J06L 制造商:BOURNS 制造商全稱(chēng):Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C3A-A12-J08L 制造商:BOURNS 制造商全稱(chēng):Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C3A-A12-J10L 制造商:BOURNS 制造商全稱(chēng):Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C3A-A12-K06 制造商:BOURNS 制造商全稱(chēng):Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
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