
4-Port 84C30A
4-45
MD400151/C
Page 31, AC Characteristics:
- Symbol TSARhas been changed to TSA.
- TSA Parameter has been changed from A
0-2
/Setup to A[3:0] Setup.
- THCS row is new.
- Symbol TWCHhas been changed to TRWH
- TRWH Parameter has been changed from RD/WR High Width, to RD High Width.
- TRWH (min) has been changed from 200 to 1 TXC/RXC Cycle.
- Symbol TWCLhas been changed to TRWL
- TRWL Parameter has been changed from RD/WR Low Width to RD Low Width.
- TRWL (min) has been changed from 200 to 1.5 TXC/RXC Cycles + 70 ns.
- TWWH row is new.
- TWWL row is new.
10/23/96
Page 4, Pin Description:
- Pin 35 Description now reads; This is the system clock acting as the chip’s ...
- Pin 39 Description now reads; This is an active high output that can be used for validating reads from the receive
FIFO during a read operation and preventing over writes to the transmit FIFO
during a write operation. For further details, please refer to the Transmit Data
Write timing and the Receive Data Read timing diagrams.
Page 12 - Section 2.0 Introduction has been deleted and replaced with new Section 2.0 Introduction.
Page 16 - Section 3.3.5 Second paragraph, now reads; Except for discards due to address mismatches and
oversized packets, all packet ...
Page 24 - Format of the Status Double Word, illustration has been added.
Page 26 - Configuration Register #1 Illustration has been changed; now reads, Bit 5 = ‘1’ Enables Full Duplex Mode
[Bit 3 should be ‘0’].
Page 28-29 - In Sections: CRC Error Counter, Runt Frame Counter, Alignment Error Counter, Transmit Collision Counter,
Receive Collision Counter; copy has changed ... To read this counter, two consecutive reads must be
performed to the same address location. The first read, reads out the high byte and the second
read, reads out the low byte. Upon reading ...
Page 30, DC Characteristics:
- Clock Input High Voltage (Limits Min.), has been changed from 3.5 to 4.0.
Pages 32 to 39, has been deleted and replaced with new Tables and Timing Diagrams, also the pagination has changed.
- Page 32, New Timing Diagrams, 5.01 Command/Status Interface Read Timing, and 5.02 Command/Status
Interface Write Timing.
- Page 33, New Timing Diagrams, 6.01 Ethernet Transmit Interface Timing, and 6.02 Ethernet Receive Interface
Timing.
- Page 33, New Table 6.0 Ethernet Transmit and Receive Interface Timing.
- Page 34, New Table, 7.0 Transmit Data Interface Timing.
- Page 35, New Timing Diagram, 7.01 Transmit Data Interface Write Timing 1.
- Page 36, New Timing Diagram, 7.02 Transmit Data Interface Write Timing 2.
- Page 37, New Table, 8.0 Receive Data Interface Timing.
- Page 38, New Timing Diagram, 8.01 Receive Data Interface Read Timing 1.
- Page 39, New Timing Diagram, 8.02 Receive Data Interface Read Timing 2.
- Page 40, New Table, 9.0 Transmit Data Interface Timing on Exception Conditions.
- Page 41, New Timing Diagram, 9.0 Transmit Data Timing on Exception Conditions.
- Page 42, New Table, 10.0 Receive Data Interface Timing on Exception Conditions.
- Page 43, New Timing Diagram, 10.0 Receive Data Timing on Exception Conditions.
12/5/96
Page 17; Internal Port Register Addressing Table
- Register Description Read, Dribble Error Counter has been changed to Alignment Error Counter.
Page 46; 208 Pin PQFP Dimension Diagram, illustration has changed.
Revision History