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參數(shù)資料
| 型號： | 84C30A |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Ethernet Controller(四端口以太網(wǎng)控制器) |
| 中文描述： | 4端口以太網(wǎng)控制器（四端口以太網(wǎng)控制器） |
| 文件頁數(shù)： | 28/46頁 |
| 文件大?。?/td> | 439K |
| 代理商： | 84C30A |
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4-Port 84C30A
4-28
MD400151/C
Fifo Threshold Register Bits
Minimum # of
Double Words of
Data for RXRDY High
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Minimum # of
Double Word Spaces
for TXRDY High
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
tains the product I.D. When the lower four bits are written
with a decimal value ranging rom 1 o 15, packet ransmis-
sion from the FIFO will begin only when the count of the
double words of data written nto the transmit FIFO equals
or exceeds twice the register value. For example, when
the lower four bits are written with a decimal value of 15,
data transmission will begin only after the FIFO is written
with 30 or more double words of data. This hreshold value
is valid only at the beginning of frame transmission and it
will take effect again when the user starts to load the
beginning of the next frame. The default decimal value of
the lower four bits is ‘0’ and packet transmission will begin
automatically when the FIFO is loaded with a minimum of
one double word of data. The upper four bits are read only
and contain a value of ‘A’.
3.7 COUNTERS
CRC Error Counter
This is a 16 bit read only counter that counts the number
of frames received or discarded with CRC errors but no
framing errors. Upon reaching ts maximum count value of
FFFF hex, this counter will stop counting. To read this
counter, two consecutive reads must be performed to the
same address location. The first read, reads out the high
byte and the second read, reads out the low byte. Upon
reading the high byte, the count value of the low byte is
frozen to prevent the ow byte count value from rolling over
3.6.6.1 FIFO Threshold Register Settings Table
before t s read. Normally, once he ow byte has been read
the counter is reset to zero. Should the 84C30A attempt
to ncrement the counter while t s frozen, then reading the
low byte of he counter causes t o be oaded with 0001 hex
thereby preventing the counter from missing a count.
Runt Frame Counter
This is a 16 bit read only counter that counts the number
of frames received or discarded less than the minimum
valid frame time (64 bytes). Upon reaching its maximum
count value of FFFF hex, his counter will stop counting. To
read this counter, two consecutive reads must be per-
formed to the same address ocation. The first read, reads
out the high byte and the second read, reads out the low
byte. Upon reading the high byte, the count value of the
low byte is frozen to prevent the low byte count value from
rolling over before it is read. Normally, once the low byte
has been read the counter is reset to zero. Should the
84C30A attempt to ncrement the counter while t s frozen,
then reading the low byte of the counter causes it to be
loaded with 0001 hex thereby preventing the counter from
missing a count.
Receive Oversize Frame Counter
This is a 8-bit counter that counts the number of receive
frames with greater than the 1518 byte maximum frame
size of data. Upon reaching ts maximum count value of FF
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 84C3A-A12-J06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J06L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J08L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J10L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-K06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
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