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參數(shù)資料
| 型號(hào)： | 84C30A |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Ethernet Controller(四端口以太網(wǎng)控制器) |
| 中文描述： | 4端口以太網(wǎng)控制器（四端口以太網(wǎng)控制器） |
| 文件頁數(shù)： | 24/46頁 |
| 文件大?。?/td> | 439K |
| 代理商： | 84C30A |
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4-Port 84C30A
4-24
MD400151/C
register clears the register and enables t to be written with
new status. The following packet status is reported in the
receive status register:
Bit 7 - Old/New status
Bit 6 - 12 bytes of a frame received.
Bit 5 - Received good frame.
Bit 4 - Oversized frame received.
Bit 3 - Short frame error.
Bit 2 - Frame with dribble bits or nibbles.
Bit 1 - Frame with CRC error.
Bit 0 - Receive FIFO overflow error.
Receive packet status is also included as part of the final
double word of receive data for a packet that is not
discarded. The final double word of a packet as read from
the receive FIFO contains the status and the byte count for
that packet with the status appearing as the least signifi-
cant word of the double word and the byte count appearing
in the two most significant bytes of the double word. The
status read through the FIFO has the same bit values as
the receive status register except for the following:
Bit 7: RXABORT During Reception
Bit 8: Read Error Condition
Bit 7 is an indication that the RXABORT pin was pulsed
HIGH while CSN was HIGH for the packet. Bit 8 Indicates
that some type of error has occurred in the receive FIFO
control circuitry with a result that the number of double
words written to the FIFO as indicated by the byte count
portion of the status double word does not equal the
number of double words read rom he FIFO or he packet.
This ype of error can only be caused by some ype of noise
glitch or other unusual occurrence within the receive
section. Any packet read from the FIFO with Bit 8 of the
Received Frame with Overflow Error
Received Frame with CRC Error
Received Frame with Dribble Error
7
6
5
3
2 1
4
0
BIT
RXABORT During Reception
Received Short Frame
Received 12 Bytes of a Frame
Received Good Frame
Received Oversize Frame
Word 0 of the Double Word
8
Read Error Condition
Format of the Status Double Word
Note:
This status double word gets appended to the
packet in same format for both Little and Big Endian
modes.
status set HIGH should be considered to have bad data.
This condition should never occur in a properly designed
application. If status s ever read with Bit 8 being HIGH, he
receive section will automatically reset itself to provide a
clean starting point for further packet reception.
Status Register Word
31
16
8
0
Reserved
Byte Count
Status Register Word
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 850-10-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 854-10-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 852-10-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 852-90-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 852-90-016-10-002 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 84C3A-A12-J06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J06L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J08L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J10L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-K06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
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