
4-Port 84C30A
4-6
6
MD400151/C
Pin Description (cont.)
Pin
Pin Name
I/O
Description
67
RXABORT_3
I
This input when pulsed high causes port #3 to abort reception of a receive frame and
clear the Receive FIFO. It can be asserted at any time during the reception of a
frame.
This input when pulsed high causes port #4 to abort reception of a receive frame and
clear the Receive FIFO. It can be asserted at any time during the reception of a
frame.
This active low input is used to set port #1 into Full Duplex Mode. In this mode the
transmitter will not defer to an active carrier sense signal.
This active low input is used to set port #2 into Full Duplex Mode. In this mode the
transmitter will not defer to an active carrier sense signal.
This active low input is used to set port #3 into Full Duplex Mode. In this mode the
transmitter will not defer to an active carrier sense signal.
This active low input is used to set port #4 into Full Duplex Mode. In this mode the
transmitter will not defer to an active carrier sense signal.
75
RXABORT_4
I
127
ADUPLX_1
I
125
ADUPLX_2
I
124
ADUPLX_3
I
123
ADUPLX_4
I
Encoder_Decoder Interface
138
TXC_1
I
This is the transmit clock input for port #1. This is a 10 Mhz, 50% duty cycle transmit
clock used to synchronize the transmit data from port #1 to the encoder. Transmit
data appears serially on the TXD0_1 output and all transitions of transmit data and
the TXEN_1 output occur from thefalling edge of the clock.
This is the transmit clock input for port #2. This is a 10 Mhz, 50% duty cycle transmit
clock used to synchronize the transmit data from port #2 to the encoder. Transmit
data appears serially on the TXD0_2 output and all transitions of transmit
data and the TXEN_2 output occur from the falling edge of the clock.
This is the transmit clock input for port #3. This is a 10 Mhz, 50% duty cycle transmit
clock used to synchronize the transmit data from port #3 to the encoder. Transmit
data appears serially on the TXD0_3 output and all transitions of transmit data and
the TXEN_3 output occur from the falling edge of the clock.
This is the transmit clock input for port #4. This is a 10 Mhz, 50% duty cycle transmit
clock used to synchronize the transmit data from port #1 to the encoder. Transmit
data appears serially on the TXD0_4 output and all transitions of transmit data and
the TXEN_4 output occur from the falling edge of the clock.
This input is the serial transmit data output from port #1 to the encoder.
This input is the serial transmit data output from port #2 to the encoder.
This input is the serial transmit data output from port #3 to the encoder.
This input is the serial transmit data output from port #4 to the encoder.
This output from port #1 is used to activate the encoder. It becomes active when the
first bit of the Preamble is transmitted and inactive when the last bit of the frame is
transmitted.
161
TXC_2
I
177
TXC_3
I
197
TXC_4
I
142
166
185
202
143
TXD_1
TXD_2
TXD_3
TXD_4
TXEN_1
O
O
O
O
O