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參數(shù)資料
| 型號： | 84C30A |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Ethernet Controller(四端口以太網(wǎng)控制器) |
| 中文描述： | 4端口以太網(wǎng)控制器（四端口以太網(wǎng)控制器） |
| 文件頁數(shù)： | 18/46頁 |
| 文件大小： | 439K |
| 代理商： | 84C30A |
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4-Port 84C30A
4-18
MD400151/C
tion register #2. Listed below are the required conditions
for a receive discard to be produced:
1. Bit 0 of the Rx command register is LOW and a
receive FIFO overflow occurred during reception.
2. Bit 1 of the Rx command register is LOW and a
packet with a CRC error was received.
3. Bit 4 of Configuration register 2 is LOW and the
RXABORT pin is driven high while CSN is high.
4. Bit 3 of he Rx command register s LOW and a packet
with less than 64 bytes of data was received.
5. Bit 4 of the Rx command register is LOW and a
packet of size greater than 1518 was received.
6. The Receiver is not in promiscuous mode and a
address mismatch occurs.
Discarding of a receive packet by a port will cause any
packet data that was written to that receive FIFO to be
flushed from the FIFO. If no completely received packets
are in the receive FIFO at the time a receive discard
occurs, the receive FIFO will be completely flushed of
data. If however, a completely received packet, as indi-
cated by the packet’s status double word having been
written to the FIFO, is in the receive FIFO at the time of a
receive discard, the FIFO will be flushed only up to the ast
completely received packet. To prevent a receive packet
from being discarded due to an error condition, you can
selectively enable the reception of errored packets as
described n the section describing bit settings on configu-
ration register #2.
Conditions that Cause the RXDC Pin to go HIGH
As packets are discarded due to the receive packet error
conditions given in the section “Description of How Re-
ceive Packets are Discarded”, the corresponding port’s
RXDC pin may or may not assert. If a receive packet’s
status has been written to the receive FIFO and the
packet’s status has not yet been read from the FIFO,
discards caused by following packets with errors are
handled within he chip and he RXDC pin will not go HIGH.
If all status double words for all packets written to the FIFO
have been read out, then the RXDC pin will go HIGH under
the following condition:
1. Enough of a receive packet has been written to the
FIFO to cause RXRDY to go HIGH before the packet
is discarded due to an error condition.
2. If there are no status double words in the receive
FIFO and if RXRDY goes HIGH just before a discard
condition occurs, RXRDY may go LOW again before
any FIFO reads have occurred. This is due to the
receive discard clearing the FIFO of any receive
bytes already written to the FIFO. In this case,
RXRDY is guaranteed to remain HIGH for at least
one RXRD_TXWR clock cycle.
Detecting and Clearing a Receive Discard Condition
To enable the output driver for the RXDC pins, the
RXINTEN input must be driven low. Once a discard
condition is detected, the receive discard can be cleared
by driving the RXINTEN input low and then pulsing the
CLRRXERR input high for a minimum of one
RXRD_TXWR clock cycle. The RXINTEN input must not
change state for the duration of the time that the
CLRRXERR input is high.
Clearing Interrupts
Within one port, both receive and transmit interrupts are
combined into a single interrupt signal which then goes to
the INT output pin. The interrupt signal in the chip is
actually the result of the receive/transmit status register
outputs and the receive/transmit command register inter-
rupt enable bits that are set. To clear an interrupt, the
status that caused the interrupt needs to be cleared. This
can be accomplished by reading the transmit status regis-
ter and/or the receive status register.
3.4 SYSTEM INTERFACE
The chip system nterface consists of one receive/transmit
32-bit bidirectional data bus, one 8-bit bidirectional com-
mand/status data bus, and each busses respective control
signals. Receive FIFO data is read and Transmit FIFO
data is written over the RXTXDATA[31:0] bus, and Com-
mand/Status data is written or read over the bidirectional
CDST[7:0] data bus.
相關(guān)PDF資料 |
PDF描述 |
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| 850-10-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 854-10-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 852-10-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 84C3A-A12-J06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J06L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J08L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J10L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-K06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
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