- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378230 > 84C30A (LSI Corporation) 4-Port Ethernet Controller(四端口以太網(wǎng)控制器) PDF資料下載
參數(shù)資料
| 型號： | 84C30A |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Ethernet Controller(四端口以太網(wǎng)控制器) |
| 中文描述： | 4端口以太網(wǎng)控制器（四端口以太網(wǎng)控制器） |
| 文件頁數(shù)： | 14/46頁 |
| 文件大小： | 439K |
| 代理商： | 84C30A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
4-Port 84C30A
4-14
MD400151/C
Scheduling of retransmission is determined by a con-
trolled randomization process called Truncated Binary
Exponential Backoff. The chip waits a random interval
between 0 and 2
K
slot times (51.2
μ
s per slot time) before
attempting retransmission, where “K” is the current trans-
mission attempt number (not to exceed 10).
3.2.4 Transmit Termination Conditions
A port will terminate transmission under the following
conditions.
Normal:
The frame has been transmitted successfully
without contention. Loading of the last data byte into a
port’s Transmit FIFO s signaled to the port by activation of
its RxTxEOF signal concurrently with the ast double word
of data loaded into the Transmit FIFO. This line acts as a
thirty-third bit in the Transmit FIFO. When the last valid
byte of the last double word has been transmitted, if the
port is not in Transmit No CRC mode, then the CRC is
appended and transmitted concluding frame transmis-
sion. The Transmission Successful bit of the Transmit
Status Register will be set by a normal termination.
Collision:
Transmission attempted by two or more Eth-
ernet nodes. The Jam sequence is transmitted, the Colli-
sion status bit s set, transmit Collision Counter s updated,
the Backoff nterval begun, and he Transmit FIFO address
is set to point to the beginning of the packet for retransmis-
sion.
Underflow:
Transmit data is not ready when needed for
transmission. Once transmission has begun, a port on
average requires one transmit double word every 3200 ns
in order to avoid Transmit FIFO underflow (starvation). If
this condition occurs, he port erminates he ransmission,
issues a TXRET signal, and sets the Transmit-Underflow
status bit.
16 Transmission Attempts:
If a Collision occurs for the
sixteenth consecutive time, the 16-Transmission-At-
tempts status bit is set, the Collision status bit is set, the
TXRET signal is generated, and the Backoff interval be-
gun. The counter that keeps track of the number of
collisions s modulo 16 and therefore rolls over on the 17th
collision. Bits 15 to 11 of a port’s transmit collision counter
allow a user o determine how many ransmission attempts
were necessary to successfully transmit the packet.
Late Collision:
If a Collision occurs greater than 64 byte
times after the transmission begins this is considered a
late collision error. Upon this condition the transmission s
terminated, the TXRET output s driven HIGH, and the ate
collision status bit is set.
At the completion of every transmission or retransmission,
new status information is loaded into the Transmit Status
Register. Dependent upon the bits enabled in the Trans-
mit Command Register, an interrupt will be generated for
the just completed transmission.
3.2.5 Conditions That Will Cause a Port’s TXRET Pin
to go High
Detection of a HIGH value on one of the chips 4 TXRET
pins indicates that the associated port could not complete
transmission of a packet due to one or more of the
following conditions:
1. A transmit FIFO underflow occurred while
transmitting the packet.
2. A late collision occurred while transmitting
the packet.
3. Carrier sense never went active during
transmission or went from an active to inactive
state during transmission.
4. 16 attempts to transmit the packet all resulted in
transmit collisions.
Any of the above conditions will cause the port to flush the
transmit FIFO and initiate a transmit retry request. With
initiation of a transmit Retry Request the port’s TXRDY
output will go low and stay low until the TXRET flag is
cleared. Similar to a port's receive discard signal, a
transmit retry signal going to the external TXRET pin is
latched upon a transmit retry condition and held high until
cleared. Until a port's transmit retry signal is cleared, no
new transmit packets can be written to the transmit FIFO.
3.2.6 Detecting and Clearing a Transmit Retry
Condition
To enable the output drivers for the four TXRET pins, the
the TXINTEN nput s driven ow. Once a Tx retry condition
is detected, that port's internal Tx retry signal can be
cleared by first setting the RXTXPS[1:0] inputs to point to
that port. Then by driving the TXINTEN input low and then
pulsing the CLRTXERR input high for a minimum of one
RXRD_TXWR clock cycle, this will clear that port's TXRET
signal. The RXTXPS [1:0] and TXINTEN inputs must not
change during the high time of the CLRTXERR input.
3.3 Packet Reception Per Port
Each port within the chip continuously monitors the net-
work. When activity is recognized via the Carrier Sense
(CSN) signal, the port will then synchronize itself to the
incoming data stream through recognition of the Start
Frame Delimiter (SFD) at the end of Preamble. The
destination address field of the frame is then examined.
Depending on the Address Match Mode specified, the port
will either recognize the frame as being addressed to tself
in a general or specific fashion or abort the frame recep-
tion. The port can also be programmed to count all colli-
sions on the network it's connected to.
相關PDF資料 |
PDF描述 |
|---|---|
| 850-10-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 854-10-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 852-10-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 852-90-016-10-001 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
| 852-90-016-10-002 | PCB connectors 1.27 mm Single row / double row / triple row Solder tail |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 84C3A-A12-J06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J06L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J08L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-J10L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C3A-A12-K06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
發(fā)布緊急采購，3分鐘左右您將得到回復。