參數(shù)資料
型號(hào)： 84C30A
廠商： LSI Corporation
英文描述： 4-Port Ethernet Controller(四端口以太網(wǎng)控制器)
中文描述： 4端口以太網(wǎng)控制器（四端口以太網(wǎng)控制器）
文件頁(yè)數(shù)： 23/46頁(yè)
文件大小： 439K
代理商： 84C30A
4-Port 84C30A
4-23
MD400151/C
Receive Command Register Format
3.6.5 Receive Command Register
A port’s Receive Command Register has two primary
functions, it specifies the Address Match Mode, and it
specifies which types of receive frames will be received
and if an associated interrupt will be produced. To set
interrupt conditions the Receive Command Register uses
bits 5 through 0 in conjunction with bit #7 of configuration
register #1.
Bit 7 of configuration register #1 is a general receive
interrupt disable. Setting this bit HIGH disables all receive
interrupt conditions even f one of the bits 0 through 5 n the
receive command register is set HIGH. This allows ena-
bling reception of receive packets with errors without an
interrupt being produced. With the general receive inter-
rupt bit LOW, a receive interrupt can be produced on one
or more of he ollowing conditions by setting ts associated
interrupt enable bit in the receive command register:
1. Interrupt on good frames
(Rx Command Bit 5)
2. Interrupt on receiving the
12 bytes of data for a
packet.
(Rx Command Bit 4)
3. Interrupt on reception of
a short frame.
(Rx Command Bit 3)
4. Interrupt on reception of
oversize frame.
(Rx Command Bit 2)
5. Interrupt on reception of
a frame with a CRC error.
(Rx Command Bit 1)
6. Interrupt on a receive FIFO
overflow error.
(Rx Command Bit 0)
For conditions 3, 4, 5 and 6 above, the associated nterrupt
enable bit also acts as a receive enable bit. This means for
example that if bit 1 of the receive command register is
written high, packets with CRC errors will be received and
no receive discard will be asserted. By using a combina-
tion of the general receive nterrupt disable bit 7 n configu-
ration register #1 and bits 0 through 3 of the receive
command register, a port can be programmed to accept
packets with error conditions without the generation of an
interrupt.
Bits 6 and 7 of the Receive Command Register are the
receive match mode bits.
Bits 0-5 specify Interrupt and Frame-of-Interest when set.
Match
Mode
1
0
0
1
Match
Mode
0
0
1
0
Function
Receiver Disable
Receive All Frames
Receive Station or Broadcast
Frames
Receive Station,
Broadcast/Multicast Frames
0
1
2
3
1
1
Match Mode Definition
Changing the receive Match Mode bits during frame re-
ception may change chip operation and give unpredictable
results.
Interrupt Enable and Frames-of-Interest
Bits 0-5 when set specify interrupt generation on occur-
rence of the corresponding frame reception condition.
3.6.6 Receive Status Register
Within each port’s receive section, here s a receive status
register that is written with the status of each receive
packet whether it is discarded or not. Once the receive
status register s written, bit 7 of he register s set o a 0 and
the register is write protected from being overwritten with
new status until it is read. Reading the receive status
Interrupt on Overflow Error
Interrupt on CRC Error
Interrupt on Oversize Frame
Match Mode 0
7
6
5
3
2 1
4
0
BIT
Match Mode 1
Interrupt on Short Frame
Interrupt on 12 Bytes Received
Interrupt on Good Frames
相關(guān)PDF資料
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854-10-016-10-001 PCB connectors 1.27 mm Single row / double row / triple row Solder tail
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
84C3A-A12-J06 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C3A-A12-J06L 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C3A-A12-J08L 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C3A-A12-J10L 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C3A-A12-K06 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
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