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| 型號(hào)： | 935263151557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP240 |
| 封裝： | 32 X 32 MM, 3.40 MM HEIGHT, MSQFP-240 |
| 文件頁(yè)數(shù)： | 174/518頁(yè) |
| 文件大小： | 7111K |
| 代理商： | 935263151557 |
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Philips Semiconductors
Arbiter
File: arb.fm5, modified 7/23/99
PRELIMINARY INFORMATION
19-5
19.5
ARBITER PROGRAMMING
The TM1100 arbiter accepts programmable bandwidth
weights to directly control the percentage of bandwidth
allocated to each unit in the worst case, in which all band-
width is used.
If not all bandwidth is used, then all units eventually get
their desired bandwidth (as the bus becomes free) re-
gardless of the weights.
However, the weights still matter to indirectly guarantee
each unit a worst-case latency, which is important for the
real-time behavior.
TM1100 units come in two flavors.
The first flavor is units which have hard real-time con-
straints, i.e. Video Out (VO), Video In (VI), Audio Out
(AO) and Audio In (AI). To assure multimedia functional-
ity, these units must be able to acquire the bus within a
fixed amount of time in order to fill or empty a buffer be-
fore it over- or underflows.
The second flavor includes the CPU, PCI, ICP, VLD and
DVDD. These units can absorb long latencies, but per-
formance is enhanced (there are fewer stall cycles or
waiting cycles) if latency is short. The bandwidth require-
ment is usually known and depends on the application. It
is especially well known for ICP and VLD or DVDD that
have a fixed bandwidth in multimedia applications.
For the TM1100 DSPCPU, latency is of prime impor-
tance. CPU performance reduces as average latency in-
creases. The design of the arbiter guarantees that the
DSPCPU gets all unused bus bandwidth with lowest pos-
sible latency. Optimal operation is achieved if the arbiter
is set in such a way that the DSPCPU has the best pos-
sible latency given the required latency and bandwidth of
units active in the application.
To pick programmable weights and priority raising delays
then, the following procedure is recommended:
1. Try to keep CPU weight as high as possible through
the remaining steps.
2. Pick weights sufcient to guarantee latency to hard
real-time peripherals (see Section 19.5.1).
3. Pick weights for remaining peripherals in order to give
enough bandwidth to each (see Section 19.5.2). Step
2 above has priority, because bandwidth can be ac-
quired as the bus becomes free and because the hard
real-time units use a known amount of bandwidth.
4. If latency and bandwidth slack remains, increase pri-
ority raise delays in order to improve average CPU la-
tency.
19.5.1
Analysis of Latency
In the following, ceil(X) is the least integral value greater
than or equal to X.
Latency is defined in each real-time unit chapter through
this data-book. Refer to the related sections to find out
the latency requirement according to the mode and clock
speed at which the device is operating.
This latency value has to be larger than the maximum la-
tency Lx (in nanoseconds) guaranteed by the arbiter.
For a device x the arbiter guarantees a latency of:
Lx = Lx,sc * (SDRAM cycle time in ns)
where
Lx,sc = (Dx * T) + E + ceil(Dx * T / Kd) * K + ceil(16*Rx/C)
is the latency in SDRAM clock cycles.
Latency in CPU clock cycles is defined by:
Lx,cc = ceil(Lx,sc * C)
The symbols are defined as follows:
T = 20 cycles (transaction length, assuming worst case
pattern alternating reads and writes).
E = 10 cycles (extra delay in case the first transaction
made by the CPU requires a different bank order to sat-
isfy the critical word first.
K = 19 cycles (refresh transaction length).
C is the CPU/SDRAM ratio (i.e. 5/4, 4/3, 3/2, 2/1 or 1 as
explained in Section 11.5.2 on page 11-3).
Rx is the priority raise delay of unit x as stored in MMIO
register ARB_RAISE (see Section 19.2).
Rx = 0 for units other than VO, VI, PCI or VLD.
Dx is the worst case number of requests that the arbiter
allows before the request from device x goes through.
Dx includes the transaction from device x (the unit which
needs the data) as well as the internal implementation
delays that occur in the transaction.
Dx is derived from the arbiter settings as follows:
D
CPU
ceil
CPU
weight
L2
weight
+
CPU
weight
-------------------------------------------------------
=
D
VO
ceil
VO
weight
L3
weight
+
VO
weight
--------------------------------------------------
D
2
×
1
+
=
D
ICP
ceil
ICP
weight
L4
weight
+
ICP
weight
----------------------------------------------------
D
3
×
1
+
=
D
VI
ceil
VI
weight
L5
weight
+
VI
weight
------------------------------------------------
D
4
×
1
+
=
D
PCI
ceil
PCI
weight
L6
weight
+
PCI
weight
-----------------------------------------------------
D
5
×
1
+
=
D
VLD
ceil
21101
++++
2
----------------------------------------
D
6
×
1
+
=
D
AI
ceil
21101
++++
1
----------------------------------------
D
6
×
1
+
=
D
AO
ceil
21101
++++
1
----------------------------------------
D
6
×
1
+
=
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