Philips Semiconductors
DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99
PRELIMINARY INFORMATION
A-163
32-bit store
pseudo-op for h_st32d(0)
SYNTAX
[ IF r
guard ] st32 rsrc1 rsrc2
FUNCTION
if r
guard then {
if PCSW.bytesex = LITTLE_ENDIAN then
bs
← 3
else
bs
← 0
mem[r
src1 + (3
⊕ bs)] ← rsrc2<7:0>
mem[r
src1 + (2
⊕ bs)] ← rsrc2<15:8>
mem[r
src1 + (1
⊕ bs)] ← rsrc2<23:16>
mem[r
src1 + (0
⊕ bs)] ← rsrc2<31:24>
}
ATTRIBUTES
Function unit
dmem
Operation code
31
Number of operands
2
Modier
No
Modier range
—
Latency
n/a
Issue slots
4, 5
DESCRIPTION
The st32 operation is a pseudo operation transformed by the scheduler into an h_st32d(0) with the same
arguments. (Note: pseudo operations cannot be used in assembly les.)
The st32 operation stores all 32 bits of r
src2 into the memory locations pointed to by the address in rsrc1. The d
value is an opcode modier and must be a multiple of 4. This store operation is performed as little-endian or big-
endian depending on the current setting of the bytesex bit in the PCSW.
If st32 is misaligned (the memory address in r
src1 is not a multiple of 4), the result of st32 is undened, and the
MSE (Misaligned Store Exception) bit in the PCSW register is set to 1. Additionally, if the TRPMSE (TRaP on
Misaligned Store Exception) bit in PCSW is 1, exception processing will be requested on the next interruptible jump.
The st32 operation can be used to access the MMIO address aperture (the result of MMIO access by 8- or 16-bit
memory operations is undened). The state of the BSX bit in the PCSW has no effect on MMIO access by st32.
The st32 operation optionally takes a guard, specied in r
guard. If a guard is present, its LSB controls the
modication of the addressed memory locations (and the modication of cache if the locations are cacheable). If the
LSB of r
guard is 1, the store takes effect. If the LSB of rguard is 0, st32 has no side effects whatever; in particular, the
LRU and other status bits in the data cache are not affected.
EXAMPLES
Initial Values
Operation
Result
r10 = 0xd00, r80 = 0x44332211
st32 r10 r80
[0xd00]
← 0x44, [0xd01] ← 0x33,
[0xd02]
← 0x22, [0xd03] ← 0x11
r50 = 0, r20 = 0xd01,
r70 = 0xaabbccdd
IF r50 st32 r20 r70
no change, since guard is false
r60 = 1, r30 = 0xd04,
r70 = 0xaabbccdd
IF r60 st32 r30 r70
[0xd04]
← 0xaa, [0xd05] ← 0xbb,
[0xd06]
← 0xcc, [0xd07] ← 0xdd
SEE ALSO
st32