Philips Semiconductors
DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99
PRELIMINARY INFORMATION
A-61
Floating-point subtract
SYNTAX
[ IF r
guard ] fsub rsrc1 rsrc2
→ rdest
FUNCTION
if r
guard then
r
dest
← (oat)rsrc1 – (oat)rsrc2
ATTRIBUTES
Function unit
falu
Operation code
113
Number of operands
2
Modier
No
Modier range
—
Latency
3
Issue slots
1, 4
DESCRIPTION
The fsub operation computes the difference r
src1–rsrc2 and writes the result into rdest. All values are in IEEE
single-precision oating-point format. Rounding is according to the IEEE rounding mode bits in PCSW. If an argument
is denormalized, zero is substituted for the argument before computing the difference, and the IFZ ag in the PCSW is
set. If the result is denormalized, the result is set to zero instead, and the OFZ ag in the PCSW is set. If fsub
causes an IEEE exception, the corresponding exception ags in the PCSW are set. The PCSW exception ags are
sticky: the ags can be set as a side-effect of any oating-point operation but can only be reset by an explicit
writepcsw
operation. The update of the PCSW exception ags occurs at the same time as r
dest is written. If any
other oating-point compute operations update the PCSW at the same time, the net result in each exception ag is the
logical OR of all simultaneous updates ORed with the existing PCSW value for that exception ag.
The fsubflags operation computes the exception ags that would result from an individual fsub.
The fsub operation optionally takes a guard, specied in r
guard. If a guard is present, its LSB controls the
modication of the destination register. If the LSB of r
guard is 1, rdest and the exception ags in PCSW are written;
otherwise, r
dest is not changed and the operation does not affect the exception ags in PCSW.
EXAMPLES
Initial Values
Operation
Result
r60 = 0xc0400000 (–3.0),
r30 = 0x3f800000 (1.0)
fsub r60 r30
→ r90
r90
← 0xc0800000 (-4.0)
r40 = 0x40400000 (3.0),
r60 = 0xc0400000 (–3.0)
fsub r40 r60
→ r95
r95
← 0x40c00000 (6.0)
r10 = 0, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e-38)
IF r10 fsub r40 r80
→ r100
no change, since guard is false
r20 = 1, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e-38)
IF r20 fsub r40 r80
→ r110
r110
← 0x40400000 (3.0), INX ag set
r40 = 0x40400000 (3.0),
r81 = 0x00400000 (5.877471754e–39)
fsub r40 r81
→ r111
r111
← 0x40400000 (3.0), IFZ ag set
r82 = 0x00c00000 (1.763241526e-38),
r83 = 0x0080000 (1.175494351e-38)
fsub r82 r83
→ r112
r112
← 0x0, OFZ ag set
r84 = 0x7f800000 (+INF),
r85 = 0x7f800000 (+INF)
fsub r84 r85
→ r113
r113
← 0xffffffff (QNaN), INV ag set
r70 = 0x7f7fffff (3.402823466e+38)
r86 = 0xff7fffff (-3.402823466e+38)
fsub r70 r86
→ r120
r120
← 0x7f800000 (+INF), OVF, INX flag
set
r87 = 0xffffffff (QNaN))
r30 = 0x3f800000 (1.0
fsub r87 r30
→ r125
r125
← 0xffffffff (QNaN)
r87 = 0xffbfffff (SNaN))
r30 = 0x3f800000 (1.0
fsub r87 r30
→ r125
r125
← 0xffffffff (QNaN), INV ag set
r83 = 0x0080001 (1.175494421e-38),
r89 = 0x0080000 (1.175494351e-38)
fsub r83 r89
→ r126
r126
← 0x0, UNF ag set
SEE ALSO
fsub