TM1100 Preliminary Data Book
Philips Semiconductors
B-2
PRELIMINARY INFORMATION
File: mmio.fm5, modified 7/23/99
INTVEC20
10 08d0
R/W
Interrupt vector (handler start address) for source 20
INTVEC21
10 08d4
R/W
Interrupt vector (handler start address) for source 21
INTVEC22
10 08d8
R/W
Interrupt vector (handler start address) for source 22
INTVEC23
10 08dc
R/W
Interrupt vector (handler start address) for source 23
INTVEC24
10 08e0
R/W
Interrupt vector (handler start address) for source 24
INTVEC25
10 08e4
R/W
Interrupt vector (handler start address) for source 25
INTVEC26
10 08e8
R/W
Interrupt vector (handler start address) for source 26
INTVEC27
10 08ec
R/W
Interrupt vector (handler start address) for source 27
INTVEC28
10 08f0
R/W
Interrupt vector (handler start address) for source 28
INTVEC29
10 08f4
R/W
Interrupt vector (handler start address) for source 29
INTVEC30
10 08f8
R/W
Interrupt vector (handler start address) for source 30
INTVEC31
10 08fc
R/W
Interrupt vector (handler start address) for source 31
TIMER1_TMODULUS
10 0c00
R/W
Contains: (maximum count value for timer 1) + 1
TIMER1_TVALUE
10 0c04
R/W
Current value of timer 1 counter
TIMER1_TCTL
10 0c08
R/W
Timer 1 control (prescale value, source select, run bit)
TIMER2_TMODULUS
10 0c20
R/W
Contains: (maximum count value for timer 2) + 1
TIMER2_TVALUE
10 0c24
R/W
Current value of timer 2 counter
TIMER2_TCTL
10 0c28
R/W
Timer 2 control (prescale value, source select, run bit)
TIMER3_TMODULUS
10 0c40
R/W
Contains: (maximum count value for timer 3) + 1
TIMER3_TVALUE
10 0c44
R/W
Current value of timer 3 counter
TIMER3_TCTL
10 0c48
R/W
Timer 3 control (prescale value, source select, run bit)
SYSTIMER_TMODULUS
10 0c60
R/W
Contains: (maximum count value for system timer) + 1
SYSTIMER_TVALUE
10 0c64
R/W
Current value of system timer/counter
SYSTIMER_TCTL
10 0c68
R/W
System timer control (prescale value, source select, run bit)
BICTL
10 1000
R/W
Instruction breakpoint control
BINSTLOW
10 1004
R/W
Start of address range that causes instruction breakpoints
BINSTHIGH
10 1008
R/W
End of address range that causes instruction breakpoints
BDCTL
10 1020
R/W
Data breakpoint control
BDATAALOW
10 1030
R/W
Start of address range that causes data breakpoints
BDATAAHIGH
10 1034
R/W
End of address range that causes data breakpoints
BDATAVAL
10 1038
R/W
Compare value for data breakpoints
BDATAMASK
10 103c
R/W
Compare mask for compare value for data breakpoints
Cache And Memory System
DRAM_CACHEABLE_LIMIT
10 0008
R/W
Start of non-cacheable region in DRAM
MEM_EVENTS
10 000c
R/W
Selects two cache-related events for counting
DC_LOCK_CTL
10 0010
R/W
Enable bit for data-cache locking, also PCI hole disable
DC_LOCK_ADDR
10 0014
R/W
Start of address range that will be locked into the data cache
DC_LOCK_SIZE
10 0018
R/W
Size of address range that will be locked into the data cache
DC_PARAMS
10 001c
R/—
Data-cache geometry (blocksize, associativity, # of sets)
IC_PARAMS
10 0020
R/—
Instruction-cache geometry (blocksize, assoc., # of sets)
MM_CONFIG
10 0100
R/—
DRAM settings (rank size, bus width, refresh interval)
ARB_BW_CTL
10 0104
R/W
Internal bus arbitration control (bandwidth/latency allocation)
ARB_RAISE
10 010C
R/W
Arbiter Priority Raising timer
POWER_DOWN
10 0108
R/W
Write to this register to initiate power down
IC_LOCK_CTL
10 0210
R/W
Enable bit for instruction-cache locking
IC_LOCK_ADDR
10 0214
R/W
Start of address range that will be locked into the instruction
cache
MMIO Register Name
Offset
(in hex)
Accessibility
Description
DSPCPU
External
PCI
Initiators