Philips Semiconductors
PCI-XIO External I/O Bus
File: pci-xio.fm5, modified 7/26/99
PRELIMINARY INFORMATION
21-5
21.3
DATA FORMATS
The data transfer formats for the PCI-XIO bus are shown
in
Figure 21-5. The 8-bit data field is the data transferred
to or from the PCI-XIO Bus. The read address is the 24-
bit address on the PCI-XIO Bus address lines when the
read transfer takes place.
21.4
INTERFACE
21.4.1
PCI-XIO Bus Interface Design
The PCI-XIO Bus can accommodate a variety of different
devices and bus protocols. The following are examples
of devices interfaced to the PCI-XIO Bus
Data
Read Address
Unused
Data
Read: XIO Bus to PCI
Write: PCI to XIO Bus
31
24 23
0
31
24 23
0
Figure 21-5. PCI-XIO Bus Data Formats
Table 21-1. PCI-XIO Bus Signal Denitions
TM1100 PCI Signal
Pins
I/O
PCI Function
XIO Function
PCI_INTB#
1
O
PCI-XIO Bus Enable = XIO Bus Active As Target Device
PCI_AD[23:0]
24
I/O
PCI Address/Data
Address bus: 16 MB
PCI_AD[31:24]
8
I/O
Data bus: 8 bits
PCI_PAR
1
O
Even Parity for AD & C/BE
PCI_C/BE0#
1
Command/Byte Enables
IORD# = Read Enable
PCI_C/BE1#
1
IOWR# = Write Enable
PCI_C/BE2#
1
DS# = Data Strobe
PCI_C/BE3#
1
unused
PCI_CLK
1
I/O
33 MHz PCI Clock: can optionally be generated by TM1100 on board osc
PCI_FRAME#
1
I/O
PCI Address/Command Strobe + Transfer In Progress
PCI_DEVSEL#
1
I/O
Device Select Valid
Asserted by TM1100 = XIO Active
PCI_IRDY#
1
I/O
Initiator Ready = Transfer In Progress
PCI_TRDY#
1
I/O
Target Ready
Asserted by TM1100 = XIO Transfer Timing
PCI_STOP#
1
I/O
Target Requests Stop of Transaction
PCI_IDSEL#
1
I
Chip Select for PCI Cong Writes
PCI_REQ#
1
O
TM1100 Requesting PCI Bus
PCI_GNT#
1
I
TM1100 Is Granted PCI Bus
PCI_PERR#
1
I
Parity Error to TM1100
PCI_SERR
1
O
System Error from TM1100
PCI_INTA#
1
I/O
General Purpose I/O
PCI_INTB#
1
I/O
General Purpose I/O
XIO Bus Active = Global Chip Select
PCI_INTC#
1
I/O
General Purpose I/O
PCI_INTD#
1
I/O
General Purpose I/O