File: intro.fm5, modified 7/23/99
PRELIMINARY INFORMATION
2-1
Overview
Chapter 2
by Gert Slavenburg
2.1
INTRODUCTION
TM1100 is a successor to the TM1000 media processor.
For those familiar with the TM1000, the new features
2.2
TM1100 FUNDAMENTALS
TM1100 is a media processor for high-performance mul-
timedia applications that deal with high-quality video and
audio. These applications can range from low-cost, ded-
icated systems such as video phones or set-top boxes to
reprogrammable, multi-purpose plug-in cards for person-
al computers. TM1100 easily implements popular multi-
media standards such as MPEG-1 and MPEG-2, but its
orientation around a powerful general-purpose CPU
(called the DSPCPU) makes it capable of implementing
a variety of multimedia algorithms, whether open or pro-
prietary. TM1100 is also easily configured in multiple pro-
cessor configurations for very high-end applications.
More than just an integrated microprocessor with unusu-
al peripherals, the TM1100 microprocessor is a fluid
computer system controlled by a small real-time OS ker-
nel that runs on the VLIW processor core. TM1100 con-
tains a DSPCPU, a high-bandwidth internal bus, and in-
ternal bus-mastering DMA peripherals.
Software compatibility between current and future Trime-
dia media processor line family members is at the
source-code and library API level; binary compatibility
between family members is not guaranteed.
TM1100
Video In
Audio In
Audio Out
I2C Interface
VLD
Coprocessor
Video Out
Timers
Synchronous
Serial
Interface
Image
Coprocessor
VLIW
CPU
16K
D$
32K
I$
CCIR656 dig. video
YUV 4:2:2
54 MHz (27 Mpix/sec)
Stereo digital audio
I2S DC–100 kHz
2/4/6/8 ch. digital audio
I2S DC–100 kHz
I2C bus to
camera, etc.
Huffman decoder
Slice-at-a-time
MPEG-1 & 2
CCIR656 digital video
YUV 4:2:2
80 MHz (40 Mpix.sec)
Analog modem or ISDN
Front End
Down & up scaling
YUV
→ RGB
50 Mpix/sec
PCI-XIO Interface
External bus
- PCI2.1 (32 bits, 33 MHz)
+ glueless 24A/8D slaves
SDRAM
Main Memory
Interface
Descrambler
Coprocessor
Figure 2-1. TM1100 block diagram.