TM1100 Preliminary Data Book
Philips Semiconductors
A-206
PRELIMINARY INFORMATION
File: ops.fm5, modified 7/23/99
Write program control and status word
SYNTAX
[ IF r
guard ] writepcsw rsrc1 rsrc2
FUNCTION
if r
guard then {
PCSW
← (PCSW & ~rsrc2) | (rsrc1 & rsrc2)
}
ATTRIBUTES
Function unit
fcomp
Operation code
161
Number of operands
1
Modier
No
Modier range
—
Latency
1
Issue slots
3
DESCRIPTION
The writepcsw copies the value of r
src1 to the PCSW (Program Control and Status Word) processor register
using rsrc2 as a mask. A bit in PCSW is affected by writepcsw only if the corresponding bit in rsrc2 is set to 1; the
value of any bit in PCSW with a corresponding 0-bit in rsrc2 will not be changed by writepcsw. Whenever a
hardware update (e.g., when a oating-point exception is raised) and a software update (through a writepcsw)
coincide, the PCSW bits currently being updated by hardware will reect the hardware-determined value while the bits
not being affected by hardware will reect the value in the writepcsw operand. The layout of PCSW is shown
below. The programmer should take care not to alter UNDEF elds in the PCSW.
Fields in the PCSW have two chief purposes: to control aspects of processor operation and to record events that
occur during program execution. Thus, writepcsw can be used to effect changes in some aspects of processor
operation and to clear elds that record events; this operation can also be used to restore state before resuming an
idled task in a multi-tasking environment. Note: The latency of writepcsw is 1, i.e. the PCSW reects the new value in
the next cycle. But it takes additional 3 cycles for updates to the exception ags and exception enable bits to take
effect in the hardware. Therefore 3 delay slots / nops shall be inserted between writepcsw and the next interruptible
jump, if exception ags or enable bits are changed. This guarantees that the new state is recognized in the interrupt
logic during execution of the ijump.
The writepcsw operation optionally takes a guard, specied in r
guard. If a guard is present, its LSB controls the
modication of PCSW. If the LSB of r
guard is 1, PCSW is written; otherwise, PCSW is unchanged.
EXAMPLES
Initial Values
Operation
Result
r30 = 0x100, r40 = 0x180
writepcsw r30 r40
PCSW.IEEE MODE = to positive innity
r20 = 0, r50 = 0x0, r60 = 0x400
IF r20 writepcsw r50 r60
no change, since guard is false
r21 = 1, r50 = 0x0, r60 = 0x400
IF r21 writepcsw r50 r60
PCSW.IEN = 0 (disable interrupts)
r70 = 0x80110000, r80 = 0xffff0000
writepcsw r70 r80
enable trap on MSE, INV and DBZ exclusively
MSE
CS
IEN
BSX
IEEE MODE
OFZ
IFZ
INV
OVF
UNF
INX
DBZ
0
1
2
3
4
5
6
7
8
9
10
11
12
14
15
Misaligned store exception
Count stalls (1
Yes)
FP exception trap-enable bits
IEEE rounding mode
0
to nearest, 1 to zero, 2 to positive, 3 to negative
Interrupt enable (1
allow interrupts)
Byte sex (1
little endian)
PCSW<31:16>
PCSW<15:0>
UNDEF
Misaligned store
exception trap enable
Trap on first exit
FP exceptions
TRP
MSE
TFE
TRP
OFZ
TRP
IFZ
TRP
INV
TRP
OVF
TRP
UNF
TRP
INX
TRP
DBZ
16
17
18
19
20
21
22
23
25
26
27
28
30
31
UNDEF
UNDEFINED
13
WBE
RSE
Write back error
Reserved exception
TRP
WBE
TRP
RSE
Write back error trap enable
Reserved exception
trap enable
29
SEE ALSO
writepcsw