TM1100 Preliminary Data Book
Philips Semiconductors
1-2
PRELIMINARY INFORMATION
File: pins.fm5, modified 7/25/99
1.5
SIGNAL PIN LIST
In the table below, a pin name ending in a ‘#’ designates an active-low signal (the active state of the signal is a low
voltage level). All other signals have active-high polarity.
Pin Name
MS
QF
P
Pad
Type
Modes
Description
Main Clock Interface
TRI_CLKIN
143
STRG3
IN
Main Input Clock. The SDRAM clock outputs (MM_CLK0 and MM_CLK1) can be set to
2x or 3x this frequency. The on-chip DSPCPU clock (DSPCPU_CLK) can be set to 1x,
5/4, 4/3, 3/2 or 2x the SDRAM clock frequency.
VDDQ
142
N/A
PWR
Quiet VDD for the PLL subsystem.
VSSQ
144
N/A
GND
Quiet VSS for the PLL subsystem.
Miscellaneous System Interface
TRI_RESET#
209
PCI
IN
TM1100 RESET input. This pin can be tied to the PCI RST# signal in PCI bus systems.
Upon receiving RESET, TM1100 initiates its boot protocol.
BOOT_CLK
146
STRG3
IN
Used for testing purposes. Must be connected to TRI_CLKIN for normal operation.
RESERVED1
145
STRG3
IN
Reserved input. Has to be connected to VDDQ for proper operation.
VREF_PCI
240
N/A
PWR
VREF_PCI must be connected to 5V for use in a 5 Volt PCI signalling environment or
to VSS (0 Volt) for use in 3.3 Volt PCI signalling environment. The supply to this pin
should be AC bypassed and provide 40 mA of DC sink or source capability. Note that
this pin can not be directly connected to the PCI ‘I/O designated power pins’ in a dual
voltage PCI plug-in card. Board level conversion circuitry is required. Refer to
Section 1.7 for the pins whose operation is affected by VREF_PCI.
VREF_PERIPH
184
N/A
PWR
VREF_PERIPH should be connected to 5V if any of the (non-PCI) inputs provided to
TM1100 are 5 Volt inputs. VREF_PERIPH should be connected to VSS (0 Volt) if all
input signals, with the possible exception of PCI signals are 3.3 Volt inputs. The supply
to this pin should be AC bypassed and provide 40 mA of DC sink or source capability.
Refer to
Section 1.7 for the pins whose operation is affected by VREF_PERIPH.
TRI_USERIRQ
147
PCI
IN
General purpose level/edge interrupt input. Vectored interrupt source number 4.
TRI_TIMER_CLK
141
PCI
IN
External general purpose clock source for timers. Max 40 MHz.
Main Memory Interface
MM_CLK0
MM_CLK1
86
83
STRG3
OUT
SDRAM Output Clock at 2x or 3x TRI_CLKIN frequency. Two identical outputs are pro-
vided to reliably drive several small memory congurations without external glue.
A series terminating resistor close to TM1100 is recommended to reduce ringing.
For driving a 50 Ohm trace, a resistor of 15 to 22 Ohm is recommended. For a higher
impedance trace, adjust accordingly.
MM_MATCHOUT
89
STRG3
OUT
Phase match clock output. This output can be used to construct an optimally sampling
MM_MATCHIN. For normal usage, tie directly to MM_MATCHIN with a minimal length
PCB trace.
MM_MATCHIN
92
NORM3
IN
Phase match clock input. Refer to MM_MATCHOUT above.
MM_A00
MM_A01
MM_A02
MM_A03
MM_A04
MM_A05
MM_A06
MM_A07
MM_A08
MM_A09
MM_A10
MM_A11
MM_A12
98
96
95
93
81
80
78
77
76
74
99
101
148
NORM3
OUT
Main memory address bus; used for row and column addresses
(pin 148 was ‘RESERVED2’ in TM1000)