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| 型號(hào)： | 935263331557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP240 |
| 封裝： | 32 X 32 MM, 3.40 MM HEIGHT, MSQFP-240 |
| 文件頁(yè)數(shù)： | 156/518頁(yè) |
| 文件大?。?/td> | 7111K |
| 代理商： | 935263331557 |
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Philips Semiconductors
Synchronous Serial Interface
File: ssi.fm5, modified 7/24/99
PRELIMINARY INFORMATION
16-9
16.10.1 SSI Control Register (SSI_CTL)
SSI_CTL is a 32-bit read/write control register is used to direct the operation of the SSI. The value of this register after
a hardware reset is 0x00F00000.
Table 16-5. SSI Control Register (SSI_CTL) Fields.
Field
Description
TXR
Transmitter Software Reset (Bit 31). Setting TXR performs the same functions as a hardware reset. Resets all
transmitter functions. A transmission in progress is interrupted and the data remaining in the TxSR is lost. The
TxFIFO pointers are reset and the data contained will not be transmitted, but the data in the SSI_TxDR and/or
TxFIFO is not explicitly deleted. The transmitter status and interrupts are all cleared. This is an action bit. This bit
always reads ‘0’. Writing a ‘1’ in combination with writing a ‘1‘ in the RXR eld will initiate a reset for the SSI module.
Note: always set together with RXR, as a separate transmitter or receiver reset is not implemented.
RXR
SSI_CTL Receiver Software Reset (Bit 30). Setting RXR performs the same functions as a hardware reset. Resets
all receiver functions. A reception in progress is interrupted and the data collected in the RxSR is lost. The RxFIFO
pointers are reset and the SSI will not generate an interrupt to DSPCPU to retrieve data in the SSI_RxDR and/or
RxFIFO. The data in the SSI_RxDR and/or RxFIFO is not explicitly deleted. The receiver status and interrupts are
all cleared.This is an action bit.This bit always reads ‘0’. Writing a ‘1’ in combination with writing a ‘1‘ in the TXR eld
will initiate a reset for the SSI module. Note: always set together with TXR, as a separate transmitter or receiver
reset is not implemented.
TXE
Transmitter Enable (Bit 29). TXE enables the operation of the transmit shift register state machine. When TXE is set
and a frame sync is detected, the transmit state machine of the SSI is begins transmission of the frame. When TXE
is cleared, the transmitter will be disabled after completing transmission of data currently in the TxSR. The serial out-
put (SSI_TxDATA) is three-stated, and any data present in SSI_TxDR and/or TxFIFO will not be transmitted (i.e., data
can be written to SSI_TxDR with TXE cleared; TDE can be cleared, but data will not be transferred to the TxSR).
Status elds updated by the Transmit state machine are not updated or reset when an active transmitter is disabled.
RXE
Receive Enable (Bit 28). When RXE is set, the receive state machine of the SSI is enabled. When this bit is cleared,
the receiver will be disabled by inhibiting data transfer into SSI_RxDR and/or RxFIFO. If data is being received while
this bit is cleared, the remainder of that 16-bit word will be shifted in and transferred to the SSI RxFIFO and/or
SSI_RxDR.
Status elds updated by the Receive state machine are not updated or reset when an active receiver is disabled.
TCP
Transmit Clock Polarity (Bit 27). The TCP bit value should only be changed when the transmitter is disabled. TCP
controls on which edge of TxCLK data is output.. TCP=0 causes data to be output at rising edge of TxCLK, TCP=1
causes data to be output at falling edge of TxCLK.
RCP
Receive Clock Polarity (Bit 26). RCP controls which edge of RxCLK samples data. This bit causes the data to be
sampled at rising edge when RCP equals one or falling edge when RCP equals zero.
TSD
Transmit Shift Direction (Bit 25). TSD controls the shift direction of transmit shift register (TxSR). Transmit data is
transmitted MSB rst when TSD is zero or LSB rst otherwise. The operation of this bit is explained in more detail in
section 16.8.
RSD
Receive Shift Direction (Bit 24). The RSD bit value should only be changed when the receiver is disabled. RSD con-
trols the shift direction of receive shift register (RxSR). Receive data is received MSB rst when RSD equals zero,
LSB rst otherwise. The operation of this bit is explained in more detail in section 16.8.
IO1
Mode Select SSI_IO1 pin (Bit 23-22). The IO1 eld value should only be changed when the transmitter and receiver
are disabled. The IO1[1:0] bits are used to select the function of SSI_IO1 pin. The function may be selected as listed
in table Table 16-6.
IO2
Mode Select SSI_IO2 pin (Bit 21-20). The IO2 eld value should only be changed when the transmitter and receiver
are disabled. The IO2[1:0] bits are used to select the function of SSI_IO2 pin. The function may be selected according
to Table 16-7
WIO1
Write IO1 (Bit 19). Value written here appears on the SSI_IO1 pin when this pin is congured to be a general purpose
output.
WIO2
Write IO2 (Bit 18). Value written here appears on the SSI_IO2 pin when this pin is congured to be a general purpose
output.
TIE
Transmit Interrupt Enable (Bit 17). Enables interrupt by the TDE ag in the SSI status register (transmit needs rell)
Also enables interrupt the TUE (transmitter underrun error) and TXFES (transmit framing error)
RIE
Receive Interrupt Enable (Bit 16). When RIE is set, the DSPCPU will be interrupted when RDF in the SSI status reg-
ister is set (receive is complete). It will also be interrupted on ROE (receiver overrun error), and on RXFES (receive
framing error).
FSS
Frame Size Select (Bits 15-12). The FSS[3:0] bits control the divide ratio for the programmable frame rate divider
used to generate the frame sync pulses. The valid setup value ranges from 1 to 16 slot(s). The value 16 is accom-
plished by storing a 0 in this eld.
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