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| 型號(hào)： | 935263331557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP240 |
| 封裝： | 32 X 32 MM, 3.40 MM HEIGHT, MSQFP-240 |
| 文件頁(yè)數(shù)： | 64/518頁(yè) |
| 文件大?。?/td> | 7111K |
| 代理商： | 935263331557 |
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TM1100 Preliminary Data Book
Philips Semiconductors
10-12
PRELIMINARY INFORMATION
File: pci.fm5, modified 7/23/99
IE (ICP DMA Enable).This bit is must be set to one to al-
low the Image Coprocessor (ICP) to write pixel data
through the PCI interface. If this bit is cleared to zero, the
ICP is not allowed to use the PCI interface. Programming
of ICP DMA is described in Section 13.6, “Operation and
HE (Host enable). This bit is initialized to zero, which
prevents the DSPCPU from serving as the host CPU in
the PCI system. If this bit is set to one, the Enable Mas-
tering (EM) bit in the PCI Configuration register (see Sec-
tion 10.6.3, “Command Register”) is also set to one
(since TM1100 must be enabled to serve as a PCI bus
initiator to perform PCI configuration).
CR (PCI Clear Reset). This bit releases the DSPCPU
from its reset state. The TM1100 device driver (executing
on an external host CPU) sets this bit to one after it com-
pletes TM1100’s configuration.
SR (PCI Set Reset). This bit forces the DSPCPU into its
reset state. Writing one to this bit resets the CPU; writing
zero causes no action. The TM1100 device driver (exe-
cuting on an external host CPU) can set this bit to reset
the DSPCPU. This form of reset resets only CPU and
Icache. The Dcache is NOT reset, nor are any peripher-
als.
RMD (Read Multiple Disable). In default operating
mode, the RMD bit should be set to zero. In that case, the
BIU uses “memory read multiple” PCI transactions for
BIU DMA, and “memory read” PCI transactions for
DSPCPU reads to PCI space. If the RMD bit is set, DMA
transactions are forced to also use the - less efficient -
“memory read” transactions. Note that TM1000 only
used “memory read” transactions.
10.7.6
PCI_ADR Register
The 30-bit PCI_ADR register is intended to be written
only by the data cache. PCI_ADR participates in the spe-
cial two-cycle data-cache-to-PCI protocol. See Section
10.7.7, “PCI_DATA Register,” for more information.
Only the DSPCPU can write to PCI_ADR. External PCI
initiators can neither read nor write this register.
DSPCPU software should not write to this register (by
writing to PCI_ADR in MMIO space). This register is in-
tended only to support the special protocol between the
data cache and PCI bus. An unexpected write to
PCI_ADR via MMIO space will not be prevented by hard-
ware and may result in data corruption on the PCI bus.
10.7.7
PCI_DATA Register
The 32-bit PCI_DATA register is intended to be used
only by the data cache. PCI_DATA participates in the
special two-cycle data-cache-to-PCI protocol.
The PCI_DATA and PCI_ADR registers are used togeth-
er by the data cache to perform a single data phase PCI
memory-space read or write. A read operation is trig-
gered when the data cache has written the transaction
address into PCI_ADR and asserted the internal signal
pci_read_operation (a direct internal connection be-
tween the data cache and PCI interface). A write opera-
tion is triggered when the data cache has written both
PCI_ADR
and
PCI_DATA
with
the
signal
pci_read_operation deasserted.
While the PCI interface is performing the PCI read or
write, the DSPCPU is stalled waiting for the completion
of the PCI transaction. When the PCI transaction is com-
plete, the PCI interface asserts pci_ready (a direct inter-
nal connection between the data cache and PCI inter-
face). To finish a read operation, the data cache reads
the PCI_DATA register, forwards the data to the
DSPCPU, and then unlocks the DSPCPU. To finish a
write, the data cache simply unlocks the DSPCPU.
Note that, if the DSPCPU attempts to access a non-exis-
tent PCI address, a RMA condition occurs. In this case,
the value in the PCI_DATA register is set to 0. Hence, the
DSPCPU always reads non-existent PCI locations as ze-
ro.
Normal MMIO write operations to PCI_DATA have no ef-
fect. Reads return the register’s current value. External
PCI initiators can neither read nor write this register.
10.7.8
CONFIG_ADR Register
The CONFIG_ADR register is written by the DSPCPU to
set up for a configuration cycle. When TM1100 is acting
as the host CPU, it must configure devices on the PCI
bus. The DSPCPU writes CONFIG_ADR to select a con-
figuration register within a specific PCI device. See Sec-
tion 10.7.10, “CONFIG_CTL Register,” for more infor-
mation on initiating configuration cycles.
Following are descriptions of the fields of CONFIG_ADR.
BN (PCI Bus Number). The BN field (the two least-sig-
nificant bits of CONFIG_ADR) selects one of four possi-
ble PCI buses. A value of zero for BN means that the tar-
geted device is on the PCI bus directly connected to
TM1100 and that any PCI-to-PCI bridges should ignore
the configuration address. Any value for BN other than
zero means that the targeted device is on a PCI bus con-
nected to a PCI-to-PCI bridge and that all devices direct-
ly connected to TM1100’s local PCI bus should ignore
the configuration address.
RN (Register Number). The RN field (bits 2..7 of
CONFIG_ADR) is used to specify one of the 64 configu-
ration words within the target device’s configuration
space.
FN (Function Number). The FN field (bits 8..10 of
CONFIG_ADR) is used to specify one of up to eight func-
tions of the addressed PCI device.
Table 10-14. IntE Bit Functions
BIU_CTL Bit
If Set to One, Interrupt DSPCPU When...
2
cong_cycle done
3
io_cycle done
4
dma_cycle done
5
pci_dram write cycle done
6
second cong_cycle or io_cycle requested
7
second dma_cycle requested
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