Philips Semiconductors
DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99
PRELIMINARY INFORMATION
A-89
IEEE status ags from convert oating-point to
integer with round toward zero
SYNTAX
[ IF r
guard ] ifixrzflags rsrc1
→ rdest
FUNCTION
if r
guard then
r
dest
← ieee_ags((long) ((oat)rsrc1))
ATTRIBUTES
Function unit
falu
Operation code
129
Number of operands
1
Modier
No
Modier range
—
Latency
3
Issue slots
1, 4
DESCRIPTION
The ifixrzflags operation computes the IEEE exceptions that would result from converting the single-precision
IEEE oating-point value in r
src1 to a signed integer, and an integer bit vector representing the computed exception
ags is written into r
dest. The bit vector stored in rdest has the same format as the IEEE exception bits in the PCSW.
The exception ags in PCSW are left unchanged by this operation. Rounding toward zero is performed; the IEEE
rounding mode bits in PCSW are ignored. If r
src1 is denormalized, zero is substituted before computing the
conversion, and the IFZ bit in the result is set.
The ifixrzflags operation optionally takes a guard, specied in r
guard. If a guard is present, its LSB controls
the modication of the destination register. If the LSB of r
guard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values
Operation
Result
r30 = 0x40400000 (3.0)
ifixrzflags r30
→ r100
r100
← 0
r35 = 0x40247ae1 (2.57)
ifixrzflags r35
→ r102
r102
← 0x02 (INX)
r10 = 0,
r40 = 0xff4fffff (–3.402823466e+38)
IF r10 ifixrzflags r40
→ r105
no change, since guard is false
r20 = 1,
r40 = 0xff4fffff (–3.402823466e+38)
IF r20 ifixrzflags r40
→ r110
r110
← 0x10 (INV)
r45 = 0x7f800000 (+INF))
ifixrzflags r45
→ r112
r112
← 0x10 (INV)
r50 = 0xbfc147ae (-1.51)
ifixrzflags r50
→ r115
r115
← 0x02 (INX)
r60 = 0x00400000 (5.877471754e-39)
ifixrzflags r60
→ r117
r117
← 0x20 (IFZ)
r70 = 0xffffffff (QNaN)
ifixrzflags r70
→ r120
r120
← 0x10 (INV)
r80 = 0xffbfffff (SNaN)
ifixrzflags r80
→ r122
r122
← 0x10 (INV)
OFZ
IFZ
INV
OVF
UNF
INX
DBZ
0
1
2
3
4
5
6
7
31
00
SEE ALSO
ixrzags