Philips Semiconductors
DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99
PRELIMINARY INFORMATION
A-69
Hardware 16-bit store with displacement
SYNTAX
[ IF r
guard ] h_st16d(d) rsrc1 rsrc2
FUNCTION
if r
guard then {
if PCSW.bytesex = LITTLE_ENDIAN then
bs
← 1
else
bs
← 0
mem[r
src2 + d + (1
⊕ bs)] ← rsrc1<7:0>
mem[r
src2 + d + (0
⊕ bs)] ← rsrc1<15:8>
}
ATTRIBUTES
Function unit
dmem
Operation code
30
Number of operands
2
Modier
7 bits
Modier range
–128..126 by 2
Latency
n/a
Issue slots
4, 5
DESCRIPTION
The h_st16d operation stores the least-signicant 16-bit halfword of r
src1 into the memory locations pointed to by
the address in r
src2 + d. The d value is an opcode modier, must be in the range –128 and 126 inclusive, and must be
a multiple of 2. This store operation is performed as little-endian or big-endian depending on the current setting of the
bytesex bit in the PCSW.
If h_st16d is misaligned (the memory address computed by r
src2 + d is not a multiple of 2), the result of
h_st16d
is undened, and the MSE (Misaligned Store Exception) bit in the PCSW register is set to 1. Additionally, if
the TRPMSE (TRaP on Misaligned Store Exception) bit in PCSW is 1, exception processing will be requested on the
next interruptible jump.
The h_st16d operation optionally takes a guard, specied in r
guard. If a guard is present, its LSB controls the
modication of the addressed memory locations (and the modication of cache if the locations are cacheable). If the
LSB of r
guard is 1, the store takes effect. If the LSB of rguard is 0, h_st16d has no side effects whatever; in particular,
the LRU and other status bits in the data cache are not affected.
EXAMPLES
Initial Values
Operation
Result
r10 = 0xcfe, r80 = 0x44332211
h_st16d(2) r80 r10
[0xd00]
← 0x22, [0xd01] ← 0x11
r50 = 0, r20 = 0xd05,
r70 = 0xaabbccdd
IF r50 h_st16d(–4) r70 r20
no change, since guard is false
r60 = 1, r30 = 0xd06,
r70 = 0xaabbccdd
IF r60 h_st16d(–4) r70 r30
[0xd02]
← 0xcc, [0xd03] ← 0xdd
SEE ALSO
h_st16d