
Philips Semiconductors
Audio Out
File: aout.fm5, modified 7/24/99
PRELIMINARY INFORMATION
9-5
Note that frames are generated (externally or internally)
even when TRANS_ENABLE de-asserted. Writes to
CC1
and
CC2
should
only
be
done
after
TRANS_ENABLE is asserted. The ‘first’ CC values will
then go out on the next frame. Writes to CC1 or CC2 be-
fore TRANS_ENABLE can result in erroneous behav-
iour.
9.8
MEMORY DATA FORMATS
The Audio Out unit autonomously reads samples from
memory in mono and stereo eight- and 16-bit-per-sam-
ple formats, as shown in
Figure 9-5. Successive samples
are always read from increasing memory address loca-
tions. The setting of the LITTLE_ENDIAN bit in the
AO_CTL register determines how increasing memory
addresses map to byte positions within words. Refer to
for details on byte ordering con-
ventions.
The Audio Out unit hardware implements a double buff-
ering scheme to ensure that there are always samples
available to transmit, even if the DSPCPU is highly load-
ed and slow to respond to interrupts. The DSPCPU soft-
ware assigns buffers by writing a base address and size
to the MMIO control fields described in
Figure 9-6. Refer
for details on
hardware/software synchronization.
In eight-bit transmit modes, data is MSB-aligned and ex-
tended with zeros before it is transmitted to the parallel
to serial converter. If SIGN_CONVERT is set to one, the
MSB of the data is inverted, which is equivalent to trans-
lating from offset binary representation to two’s comple-
ment. This allows the use of an external two’s comple-
ment 16-bit D/A converter to generate audio from eight-
bit unsigned samples.
Note that the Audio Out hardware does
not generate A-
law or
-law eight-bit data formats. If such formats are
desired, the DSPCPU can be used to convert from A-law
or
-law data to 16-bit linear data.
Table 9-6. Audio Out MMIO Codec Control/Status
elds
Field Name
Description
CC1 (16)
The 16-bit value of CC1 is shifted into each
emitted serial frame starting at bit position
CC1_POS, as long as CC1_EN is asserted.
Only write to CC1 if TRANS_ENABLE is set.
CC1_POS
Denes the bit position within a serial frame
where the rst data bit of CC1 is placed.
RESET Default 0.
CC1_EN
0
CC1 emission disabled (RESET default)
1
CC1 emission enabled.
CC2(16)
The 16-bit value of CC2 is shifted into each
emitted serial frame starting at bit position
CC2_POS, as long as CC2_EN is asserted.
Only write to CC2 if TRANS_ENABLE is set.
CC2_POS
Denes the bit position within a serial frame
where the rst data bit of CC2 is placed.
Default 0.
CC2_EN
0
CC2 emission disabled (RESET default)
1
CC2 emission enabled.
CC_BUSY
0
Audio Out is ready to receive a CC1,
CC2 pair (RESET default).
1
Audio Out is not ready to receive a CC1,
CC2 pair. Try again in a few AO_SCK
clock intervals.
Figure 9-5. Audio Out memory DMA formats.
adr
leftn
adr+1
leftn+1
adr+2
leftn+2
adr+3
leftn+3
adr+4
leftn+4
adr+5
leftn+5
adr+6
leftn+6
adr+7
leftn+7
8-bit
mono
adr
leftn
adr+1
rightn
adr+2
leftn+1
adr+3
rightn+1
adr+4
leftn+2
adr+5
rightn+2
adr+6
leftn+3
adr+7
rightn+3
8-bit
stereo
16-bit
mono
leftn
adr
leftn+1
adr+2
leftn+2
adr+4
leftn+3
adr+6
16-bit
stereo
leftn
adr
rightn
adr+2
leftn+1
adr+4
rightn+1
adr+6