Philips Semiconductors
DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99
PRELIMINARY INFORMATION
A-47
Floating-point compare greater
SYNTAX
[ IF r
guard ] fgtr rsrc1 rsrc2
→ rdest
FUNCTION
if r
guard then {
if (oat)r
src1 > (oat)rsrc2 then
r
dest
← 1
else
r
dest
← 0
}
ATTRIBUTES
Function unit
fcomp
Operation code
144
Number of operands
2
Modier
No
Modier range
—
Latency
1
Issue slots
3
DESCRIPTION
The fgtr operation sets the destination register, r
dest, to 1 if the rst argument, rsrc1, is greater than the second
argument, r
src2; otherwise, rdest is set to 0. The arguments are treated as IEEE single-precision oating-point values;
the result is an integer. If an argument is denormalized, zero is substituted for the argument before computing the
comparison, and the IFZ ag in the PCSW is set. If fgtr causes an IEEE exception, the corresponding exception
ags in the PCSW are set. The PCSW exception ags are sticky: the ags can be set as a side-effect of any oating-
point operation but can only be reset by an explicit writepcsw operation. The update of the PCSW exception ags
occurs at the same time as r
dest is written. If any other oating-point compute operations update the PCSW at the
same time, the net result in each exception ag is the logical OR of all simultaneous updates ORed with the existing
PCSW value for that exception ag.
The fgtrflags operation computes the exception ags that would result from an individual fgtr.
The fgtr operation optionally takes a guard, specied in r
guard. If a guard is present, its LSB controls the
modication of the destination register. If the LSB of r
guard is 1, rdest and the exception ags in PCSW are written;
otherwise, r
dest is not changed and the operation does not affect the exception ags in PCSW.
EXAMPLES
Initial Values
Operation
Result
r30 = 0x40400000 (3.0), r40 = 0 (0.0)
fgtr r30 r40
→ r80
r80
← 1
r30 = 0x40400000 (3.0)
fgtr r30 r30
→ r90
r90
← 0
r10 = 0, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0)
IF r10 fgtr r60 r30
→ r100
no change, since guard is false
r20 = 1, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0)
IF r20 fgtr r60 r30
→ r110
r110
← 0
r30 = 0x40400000 (3.0),
r60 = 0x3f800000 (1.0)
fgtr r30 r60
→ r120
r120
← 1
r30 = 0x40400000 (3.0),
r61 = 0xffffffff (QNaN)
fgtr r30 r61
→ r121
r121
← 0, INV ag set
r50 = 0x7f800000 (+INF)
r55 = 0xff800000 (-INF)
fgtr r50 r55
→ r125
r125
← 1
r60 = 0x3f800000 (1.0),
r65 = 0x00400000 (5.877471754e-39)
fgtr r60 r65
→ r126
r126
← 1, IFZ ag set
r50 = 0x7f800000 (+INF)
fgtr r50 r50
→ r127
r127
← 0
SEE ALSO
fgtr