參數(shù)資料
型號(hào)： AM79C971
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
中文描述： PCnet⑩快速單芯片全雙工10/100 Mbps以太網(wǎng)控制器，PCI總線
文件頁(yè)數(shù)： 173/265頁(yè)
文件大小： 3190K
代理商： AM79C971
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Am79C971
173
P R E L I M I N A R Y
7-0
SRAM_SIZE SRAM Size. Specifies the upper
8 bits of the 16-bit total size of the
SRAM
SRAM_SIZE accounts for a 512-
byte page. The starting address
for the lower 8 bits is assumed to
be 00h and the ending address
for the lower is assumed to be
FFh. Therefore, the maximum ad-
dress range is the starting ad-
dress of 0000h to ending address
of ((SRAM_SIZE +1) * 256
words)
SRAM_SIZE value of all zeros
specifies that no SRAM is present
and the internal FIFOs will be
joined into a contiguous FIFO
similar to the PCnet-PCI II con-
troller.
buffer.
Each
bit
in
or
FFFFh.
An
Note
: The minimum allowed
number of pages is eight for nor-
mal network operation. The
Am79C971 controller will not op-
erate correctly with less than the
eight pages of memory. When
the minimum number of pages is
used, these pages must be allo-
cated four each for transmit and
receive. Also note that a
“
No
SRAM configuration
”
is only valid
for 10Mb mode. In 100Mb mode,
SRAM is mandatory and must al-
ways be used.
CAUTION:
SRAM_BND and SRAM_SIZE
to the same value will cause
data corruption except in the
case where SRAM_SIZE is 0.
Programming
Read accessible always; write
accessible only when the STOP
bit is set. SRAM_SIZE is set to
000000b during H_RESET and is
unaffected by S_RESET or
STOP.
BCR26: SRAM Boundary Register
Bit
Name
Description
Note: Bits 7-0 in this register are programmable
through the EEPROM.
31-8
RES
Reserved locations. Written as
zeros and read as undefined.
7-0
SRAM_BND
SRAM Boundary. Specifies the
upper 8 bits of the 16-bit address
boundary where the receive buffer
begins in the SRAM. The transmit
buffer in the SRAM begins at ad-
dress 0 and ends at the address
located just before the address
specified by SRAM_BND. There-
fore, the receive buffer always be-
gins on a 512 byte boundary. The
lower bits are assumed to be ze-
ros. SRAM_BND has no effect in
the Low Latency Receive mode.
Note
: The minimum allowed
number of pages is four. The
Am79C971 controller will not op-
erate correctly with less than four
pages of memory per queue. See
Table 37 for SRAM_BND pro-
gramming details.
Table 37.
SRAM_BND Programming
CAUTION:
SRAM_BND and SRAM_SIZE
to the same value will cause
data corruption except in the
case where SRAM SIZE is 0.
Programming
Read accessible always; write
accessible only when the STOP
bit is set. SRAM_BND is set to
00000000b during H_RESET
and is unaffected by S_RESET or
STOP.
BCR27: SRAM Interface Control Register
Note:
Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15
PTR TST
Reserved. Reserved for manu-
facturing tests. Written as zero
and read as undefined.
SRAM Addresses
Minimum
SRAM_BND
address
Maximum
SRAM_BND
address
SRAM_BND
[7:0]
Lower Address
[7:0]
04h
00-FFh
FCh
00-FFh
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參數(shù)描述
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