96
Am79C971
Note:
*Lowest EEPROM address.
Table 13.
EEPROM Content
Byte
Addr.
Word
Address
Byte
Addr.
Most Significant Byte
Least Significant Byte
00h*
01h
2nd byte of the ISO 8802-3 (IEEE/ANSI
802.3) station physical address for this
node
00h
First byte of the ISO 8802-3 (IEEE/ANSI 802.3)
station physical address for this node, where
“
first
byte
”
refers to the first byte to appear on the 802.3
medium
3rd byte of the node address
5th byte of the node address
Reserved location must be 00h
01h
02h
03h
03h
05h
07h
4th byte of the node address
6th byte of the node address
reserved location: must be 00h
Hardware ID: must be 11h if compatibility
to AMD drivers is desired
User programmable space
MSB of two-byte checksum, which is the
sum of bytes 00h-0Bh and bytes 0Eh and
0Fh
Must be ASCII
“
W
”
(57h) if compatibility
to AMD driver software is desired
BCR2[15:8] (Miscellaneous
Configuration)
BCR4[15:8] (Link Status LED)
BCR5[15:8] (LED1 Status)
BCR6[15:8] (LED2 Status)
BCR7[15:8] (LED3 Status)
BCR9[15:8] (Full-Duplex Control)
BCR18[15:8] (Burst and Bus Control)
BCR22[15:8] (PCI Latency)
BCR23[15:8] (PCI Subsystem Vendor
ID)
BCR24[15:8] (PCI Subsystem ID)
BCR25[15:8] (SRAM Size)
BCR26[15:8] (SRAM Boundary)
BCR27[15:8] (SRAM Interface Control)
BCR32[15:8] (MII Control and Status)
BCR33[15:8] (MII Address)
BCR35[15:8] (PCI Vendor ID)
Reserved location must be 00h
Reserved location must be 00h
Reserved location must be 00h
Reserved location must be 00h
Reserved location must be 00h
Reserved location must be 00h
Reserved location must be 00h
Checksum adjust byte for the 64 bytes of
the EEPROM contents, checksum of the
64 bytes of the EEPROM should total to
FFh
02h
04h
06h
04h
09h
08h
Reserved location must be 00h
05h
0Bh
0Ah
User programmable space
06h
0Dh
0Ch
LSB of two-byte checksum, which is the sum of bytes
00h-0Bh and bytes 0Eh and 0Fh
07h
0Fh
0Eh
Must be ASCII
“
W
”
(57h) if compatibility to AMD driver
software is desired
08h
11h
10h
BCR2[7:0] (Miscellaneous Configuration)
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
13h
15h
17h
19h
1Bh
1Dh
1Fh
12h
14h
16h
18h
1Ah
1Ch
1Eh
BCR4[7:0] (Link Status LED)
BCR5[7:0] (LED1 Status)
BCR6[7:0] (LED2 Status)
BCR7[7:0] (LED3 Status)
BCR9[7:0] (Full-Duplex Control)
BCR18[7:0] (Burst and Bus Control)
BCR22[7:0] (PCI Latency)
10h
21h
20h
BCR23[7:0] (PCI Subsystem Vendor ID)
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
23h
25h
27h
29h
2Bh
2Dh
2Fh
31h
33h
35h
37h
39h
3Bh
3Dh
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
36h
38h
3Ah
3Ch
BCR24[7:0] (PCI Subsystem ID)
BCR25[7:0] (SRAM Size)
BCR26[7:0] (SRAM Boundary)
BCR27[7:0] (SRAM Interface Control)
BCR32[7:0] (MII Control and Status)
BCR33[7:0] (MII Address)
BCR35[7:0] (PCI Vendor ID)
Reserved location must be 00h
Reserved location must be 00h
Reserved location must be 00h
Reserved location must be 00h
Reserved location must be 00h
Reserved location must be 00h
Reserved location must be 00h
1Fh
3Fh
3Eh
Reserved location must be 00h