- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄366550 > AM79C971 (Advanced Micro Devices, Inc.) PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus PDF資料下載
參數(shù)資料
| 型號(hào)： | AM79C971 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
| 中文描述： | PCnet⑩快速單芯片全雙工10/100 Mbps以太網(wǎng)控制器，PCI總線 |
| 文件頁(yè)數(shù)： | 256/265頁(yè) |
| 文件大小： | 3190K |
| 代理商： | AM79C971 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)當(dāng)前第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)
F-4
Workaround:
Do not allow a chain of TX descriptors to include a descriptor which previously was an end of
chain (EOP) and which is the last TX EOP descriptor for which the status has been returned. Here is a sug-
gested method for the workaround:
The device driver
’
s TX Write pointer (TX_W) points to first TX descriptor with OWN = 0
The device driver
’
s TX Read pointer (TX_R) points to the last TX descriptor with OWN=0
As the TX_R pointer is advancing in the chain, if the EOP bit is set then set a device driver TX_Last
EOP pointer (TX_L) = Current TX_R pointer
Then when a new frame is to be transmitted:
1) If a single descriptor is needed
if TX_R >TX_W, then a descriptor is available
2) If buffer chaining
if TX_L =TX_W, then TX_R -TX_W descriptors are available
else only TX_L - TX_W descriptors are available
Status:
No current plan to fix this erratum
.
16)
Symptom:
Collision LED does not show the collision status of the MII bus.
Implication:
Very minor, collision LED will not show the status.
Workaround:
None.
Status:
No current plan to fix this erratum
.
17)
Symptom:
During the automatic read of the EEPROM, such as after hardware reset or when the PREAD bit
is set in the BCR19, the device drives the EECS and EESK signal pins simultaneously. The EECS is driven
high at the same time when the EESK is driving low. This violates the EEPROM clock low to chip select setup
time (tSKS) parameter, which should be 100ns.
Implication:
None. Even though the tSKS parameter is technically violated, the relationship between EESK
(clock), EECS (chip select), and EEDI (data in) signals is such that the device will not detect a false opcode.
This is how these signals relate to each other. EESK starts toggling from a high level. It clocks twice before
the EECS is asserted and continues toggling. The EEDI input is driven low at the same time that the EESK
starts toggling and stay low for four clocks after the assertion of the EECS. Since the EEDI is low when the
EECS is asserted, no false opcode is detected by the EEPROM.
Workaround:
None needed. An external circuit may be used to delay the EECS signal by 100ns from the fall-
ing edge of the EESK signal
Status:
No current plan to fix this erratum
.
AM79C971A SYSTEM DESIGN HINTS
1) In 100 Mb/s mode, if the device reports excessive Transmit Underflows, set the NOUFLO bit (BCR18, bit 11) to
1. BCR18 contents are programmable either through the EEPROM or software driver.
2) In a system which does not use the reset pulse (RST#) for a warm boot reset (also known as Ctrl-Alt-Del reset),
the PCI-SIG recommends that the BIOS should disable bus mastering capability of the PCI bus mastering de-
vices early in the reboot cycle. The disabling of the bus mastering capability can be accomplished by resetting
the BMEN bit in the PCI Command Register (bit 2, Offset 04h) of the device
’
s PCI configuration space. This
recommendation should be followed to avoid possible system hang.
3) In the 100Mb/s Full Duplex mode, the expansion bus clock (which is typically connected to the PCI bus clock)
speed needs to be at 33MHz. Any slower speed may cause under/over flow condition.
4) When in auto-polling mode and no receive descriptors are available, the transmitter will not transmit until either a
receive descriptor is available or the transmit demand bit (TDMD, CSR0, bit 3) is set. If there are no receive
descriptors available, only one packet will be transmitted for every TDMD.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C971KCW | IC LOGIC 16211 24-BIT FET BUS SWITCH -40+85C TSSOP-56 35/TUBE |
| AM79C972BKCW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972BKIW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972BVCW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972 | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C971AKC | 制造商:Advanced Micro Devices 功能描述: |
| AM79C971AVC | 制造商:Advanced Micro Devices 功能描述:10/100 MBPS ETHERNET - Trays |
| AM79C971AVC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C971AVC\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C971AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。