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參數(shù)資料
| 型號： | AM79C971 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
| 中文描述： | PCnet⑩快速單芯片全雙工10/100 Mbps以太網(wǎng)控制器，PCI總線 |
| 文件頁數(shù)： | 27/265頁 |
| 文件大?。?/td> | 3190K |
| 代理商： | AM79C971 |
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Am79C971
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the SFD (Start of Frame Delimiter) of a received frame.
Data on the RXD[3:0] will be the start of the destination
address field. SFBD will subsequently toggle every nib-
ble time (1.25 MHz frequency when operating at 10
Mbps and 12.5 MHz frequency when operating at 100
Mbps) indicating the first nibble of each subsequent
byte of the received nibble stream. The RX_CLK
should be used in conjunction with the SFBD to latch
the correct data for external address matching. SFBD
will be active only during frame reception.
Note:
The SFBD pin is multiplexed with the EESK and
LED1 pins.
When RST is active, SFBD is an input for NAND tree
testing
.
SRD
Serial Receive Data
SRD is the decoded NRZ data from the network. This
signal can be used for external address detection.
When the 10BASE-T port is selected, transitions on
SRD will only occur during receive activity. When the
AUI port is selected, transitions on SRD will occur dur-
ing both transmit and receive activity.
Input/Output
When the EADI is enabled (EADISEL, BCR2, bit 3) and
the Receive Frame Tagging is enabled (RXFRTG,
CSR7, bit 14) and the MII is selected, the SRD pin be-
comes a data input pin for the Receive Frame Tag (MI-
IRXFRTGD). See the
Receive Frame Tagging
section
for details.
Note:
When the MII port is selected, SRD will not gen-
erate transitions and receive data must be derived from
the Media Independent Interface RXD[3:0] pins.
Note also that the SRD pin is multiplexed with the
EEDO and LED3 pins
.
When RST is active, SRD is an input for NAND tree
testing
.
SRDCLK
Serial Receive Data Clock
Serial Receive Data is synchronous with reference to
SRDCLK. When the 10BASE-T port is selected, transi-
tions on SRDCLK will only occur during receive activity.
When the AUI port is selected, transitions on SRDCLK
will occur during both transmit and receive activity.
Input/Output
When the EADI is enabled (EADISEL, BCR2, bit 3), the
Receive Frame Tagging is enabled (RXFRTG, CSR7,
bit 14), and the MII is selected, the SRDCLK pin be-
comes a data input enable pin for the Receive Frame
Tag (MIIRXFRTGE). See the
Receive Frame Tagging
section for details.
Note:
When the MII port is selected, SRDCLK will not
generate transitions and the receive clock must be de-
rived from the MII RX_CLK pin.
Note also that the SRDCLK pin is multiplexed with the
LED2 pin
.
When RST is active, SRDCLK is an input for NAND
tree testing
.
RXFRTGD
Receive Frame Tag Data
When the EADI is enabled (EADISEL, BCR2, bit 3), the
Receive Frame Tagging is enabled (RXFRTG, CSR7,
bit 14), and the MII is not selected, the RXFRTGD pin
becomes a data input pin for the Receive Frame Tag.
See the
Receive Frame Tagging
section for details.
Input
Note:
The RXFRTGD pin is multiplexed with the
RXD[0] pin.
When RST is active, RXFRTGD is an input for NAND
tree testing.
RXFRTGE
Receive Frame Tag Enable
When the EADI is enabled (EADISEL, BCR2, bit 3), the
Receive Frame Tagging is enabled (RXFRTG, CSR7,
bit 14), and the MII is not selected, the RXFRTGE pin
becomes a data input enable pin for the Receive Frame
Tag. See the
Receive Frame Tagging
section for de-
tails.
Input
Note:
The RXFRTGE pin is multiplexed with the
RX_DV pin.
When RST is active, RXFRTGE is an input for NAND
tree testing.
MIIRXFRTGD
MII Receive Frame Tag Enable
When the EADI is enabled (EADISEL, BCR2, bit 3), the
Receive Frame Tagging is enabled (RXFRTG, CSR7,
bit 14), and the MII is selected, the MIIRXFRTGD pin
becomes a data input pin for the Receive Frame Tag.
See the
Receive Frame Tagging
section for details.
Input/Output
Note:
The MIIRXFRTGD pin is multiplexed with the
SRD pin.
When RST is active, MIIRXFRTGD is an input for
NAND tree testing.
MIIRXFRTGE
MII Receive Frame Tag Enable
When the EADI is enabled (EADISEL, BCR2, bit 3), the
Receive Frame Tagging is enabled (RXFRTG, CSR7,
bit 14), and the MII is selected, the MIIRXFRTGE pin
becomes a data input enable pin for the Receive Frame
Tag. See the
Receive Frame Tagging
section for de-
tails.
Input/Output
Note:
The MIIRXFRTGE pin is multiplexed with the
SRDCLK pin.
相關(guān)PDF資料 |
PDF描述 |
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| AM79C971KCW | IC LOGIC 16211 24-BIT FET BUS SWITCH -40+85C TSSOP-56 35/TUBE |
| AM79C972BKCW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972BKIW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972BVCW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972 | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C971AKC | 制造商:Advanced Micro Devices 功能描述: |
| AM79C971AVC | 制造商:Advanced Micro Devices 功能描述:10/100 MBPS ETHERNET - Trays |
| AM79C971AVC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C971AVC\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C971AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
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