參數(shù)資料
型號: AM79C971
廠商: Advanced Micro Devices, Inc.
英文描述: PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
中文描述: PCnet⑩快速單芯片全雙工10/100 Mbps以太網控制器,PCI總線
文件頁數(shù): 60/265頁
文件大?。?/td> 3190K
代理商: AM79C971
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁當前第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁第258頁第259頁第260頁第261頁第262頁第263頁第264頁第265頁
60
Am79C971
a value of 9531 (253Bh). The default value of STVAL is
FFFFh which yields the approximate maximum 838 ms
timer duration. A write to STVAL restarts the timer with
the new contents of STVAL.
Media Access Control
The Media Access Control (MAC) engine incorporates
the essential protocol requirements for operation of an
Ethernet/IEEE 802.3-compliant node, and provides the
interface between the FIFO subsystem and the
Manchester Encoder/Decoder (MENDEC) or the MII.
The MAC engine has been changed from a single-bit
wide engine into a 4-bit (nibble) wide engine. This was
done to accommodate the nibble wide MII.
This section describes operation of the MAC engine
when operating in half-duplex mode. When operating in
half-duplex mode, the MAC engine is fully compliant to
Section 4 of ISO/IEC 8802-3 (ANSI/IEEE Standard
1990 Second Edition) and ANSI/IEEE 802.3 (1985).
When operating in full-duplex mode, the MAC engine
behavior changes as described in the section
Full-
Duplex Operation
.
The MAC engine provides programmable enhanced
features designed to minimize host supervision, bus
utilization, and pre- or post-message processing.
These features include the ability to disable retries after
a collision, dynamic FCS generation on a frame-by-
frame basis, automatic pad field insertion and deletion
to enforce minimum frame size attributes, automatic re-
transmission without reloading the FIFO, and auto-
matic deletion of collision fragments.
The two primary attributes of the MAC engine are:
I
Transmit and receive message data encapsulation
Framing (frame boundary delimitation, frame
synchronization)
Addressing (source and destination address
handling)
Error detection (physical medium transmission
errors)
I
Media access management
Medium allocation (collision avoidance, except
in full-duplex operation)
Contention resolution (collision handling, except
in full-duplex operation)
Transmit and Receive Message Data Encapsulation
The MAC engine provides minimum frame size en-
forcement for transmit and receive frames. When
APAD_XMT (CSR, bit 11) is set to 1, transmit mes-
sages will be padded with sufficient bytes (containing
00h) to ensure that the receiving station will observe an
information field (destination address, source address,
length/type, data, and FCS) of 64 bytes. When
ASTRP_RCV (CSR4, bit 10) is set to 1, the receiver will
automatically strip pad bytes from the received mes-
sage by observing the value in the length field and by
stripping excess bytes if this value is below the mini-
mum data size (46 bytes). Both features can be inde-
pendently over-ridden to allow illegally short (less than
64 bytes of frame data) messages to be transmitted
and/or received. The use of this feature reduces bus
utilization because the pad bytes are not transferred
into or out of main memory.
Framing
The MAC engine will autonomously handle the con-
struction of the transmit frame. Once the transmit FIFO
has been filled to the predetermined threshold (set by
XMTSP in CSR80) and access to the channel is cur-
rently permitted, the MAC engine will commence the 7-
byte preamble sequence (10101010b, where first bit
transmitted is a 1). The MAC engine will subsequently
append the Start Frame Delimiter (SFD) byte
(10101011b) followed by the serialized data from the
transmit FIFO. Once the data has been completed, the
MAC engine will append the FCS (most significant bit
first) which was computed on the entire data portion of
the frame. The data portion of the frame consists of
destination address, source address, length/type, and
frame data. The user is responsible for the correct or-
dering and content in each of these fields in the frame.
The MAC does not use the content in the length/type
field unless APAD_XMT (CSR4, bit 11) is set and the
data portion of the frame is shorter than 60 bytes.
The receive section of the MAC engine will detect an in-
coming preamble sequence and lock to the encoded
clock. The internal MENDEC will decode the serial bit
stream and present this to the MAC engine. The MAC
will discard the first 8 bits of information before search-
ing for the SFD sequence. Once the SFD is detected,
all subsequent bits are treated as part of the frame.
During MII operation, the MAC engine will detect the in-
coming preamble sequence when the RX_DV signal is
activated by the external PHY. The MAC will discard the
preamble and begin searching for the SFD except in
the case of 100BASE-T4. In that case, the SFD will be
the first nibble across the MII interface. Once the SFD
is detected, all subsequent nibbles are treated as part
of the frame. The MAC engine will inspect the length
field to ensure minimum frame size, strip unnecessary
pad characters (if enabled), and pass the remaining
bytes through the receive FIFO to the host. If pad strip-
ping is performed, the MAC engine will also strip the re-
ceived FCS bytes, although normal FCS computation
and checking will occur. Note that apart from pad strip-
ping, the frame will be passed unmodified to the host.
If the length field has a value of 46 or greater, all frame
bytes including FCS will be passed unmodified to the
receive buffer, regardless of the actual frame length.
If the frame terminates or suffers a collision before 64
bytes of information (after SFD) have been received,
相關PDF資料
PDF描述
AM79C971KCW IC LOGIC 16211 24-BIT FET BUS SWITCH -40+85C TSSOP-56 35/TUBE
AM79C972BKCW PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
AM79C972BKIW PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
AM79C972BVCW PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
AM79C972 PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
相關代理商/技術參數(shù)
參數(shù)描述
AM79C971AKC 制造商:Advanced Micro Devices 功能描述:
AM79C971AVC 制造商:Advanced Micro Devices 功能描述:10/100 MBPS ETHERNET - Trays
AM79C971AVC\\W 制造商:Rochester Electronics LLC 功能描述:- Bulk
AM79C971AVC\W 制造商:Rochester Electronics LLC 功能描述:- Bulk
AM79C971AWW WAF 制造商:Advanced Micro Devices 功能描述: