I-5
MII Network Port Manager
MII Network Status Interface
MII Receive Interface
MII Transmit Interface
Transmit and Receive Message Data
Encapsulation
MENDEC Transmit Path
MII
MII, See Media Independent Interface
Miscellaneous Loopback Features
Mode
Modes
AUI
GPSI
T-MAU
79
77
76
76
60
70
60
69
183
72
75
69
N
Network Interfaces, Basic Functions
No SRAM Configuration, AMD Flash
Programming
Non-Burst FIFO DMA Transfers
29
92
50
O
Operating Ranges
Operating Ranges, DC Characteristics
Operation
Automatic Pad Generation
Transmit Exception Conditions
Transmit FCS Generation
Transmit Function Programming
Ordering Information
Outline, LAPP Flow
200
200
64
65
64
63
4
D-1
P
PADR
Parity Error Response
PCI (Peripheral Component Interconnect)
Command Register
Expansion ROM Base Address Register
182
35, 43
108
113
111
114
114
111
114
Header Type Register
Interrupt Line Register
Interrupt Pin Register
Latency Timer Register
MAX_LAT Register
Memory Mapped I/O Base Address
Register
MIN_GNT Register
PCI I/O Base Address Register
Programming Interface Register
Revision ID Register
Status Register
Sub-Class Register
Subsystem ID Register
Subsystem Vendor ID Register
Physical Dimensions
112
114
111
111
111
109
111
113
113
229
Pin Designations
Listed By Driver Type
Listed by Group
Listed by Pin Number
PLL Tracking
Polarity Detection and Reversal
Power Savings Modes
Magic Packet
Sleep
Power Supply Pins
Preemption
During Non-Burst Transaction
17
15
13
71
73
97
98
97
28
42
R
Receive
Descriptor Table Entry
Exception Conditions
FCS Checking
Operation
Address Matching
Automatic Pad Stripping
Exception Conditions
FCS Checking
Function Programming
Receive Descriptors
RMD0
RMD1
RMD2
RMD3
Receiver Path, Manchester Encoder/Decoder
58
68
68
66
67
68
68
66
183
183
183
185
186
71
Recommendation for Power and Ground
Decoupling
Register Programming Summary
Am79C971 Bus Configuration Registers
Am79C971 Control and Status Registers
Am79C971Programmable Registers
Related AMD Products
Reset
H_Reset
RLEN and TLEN
STOP
RMD0
RMD1
RMD2
RMD3
B-1
196
198
196
196
10
102
102
181
102
183
183
185
186
S
Signal Quality Error Test Function
Slave
Bus Interface Unit
Configuration Transfers
Slave I/O Transfers
Slave Cycle Termination
Disconnect of Burst Transfer
Parity Error Response
Sleep Mode
74
30
30
30
34
35
97